/**************************************************************************//**
 * @file     nuc970_emac.h
 * @version  V1.00
 * $Revision: 1 $
 * $Date: 22/02/11 11:49p $
 * @brief    NUC970 EMAC driver header file
 *
 * @note
 * SPDX-License-Identifier: Apache-2.0
 * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NUC970_EMAC_H__
#define __NUC970_EMAC_H__

#include "nuc970.h"

#ifdef __cplusplus
extern "C"
{
#endif

/** @addtogroup Standard_Driver Standard Driver
  @{
*/

/** @addtogroup EMAC_Driver EMAC Driver
  @{
*/

/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
  @{
*/

#define EMAC_PHY_ADDR      1UL      /*!<  PHY address, this address is board dependent \hideinitializer */
#define EMAC_RX_DESC_SIZE  64UL     /*!<  Number of Rx Descriptors, should be 2 at least \hideinitializer */
#define EMAC_TX_DESC_SIZE  32UL     /*!<  Number of Tx Descriptors, should be 2 at least \hideinitializer */
#define EMAC_CAMENTRY_NB   16UL     /*!<  Number of CAM \hideinitializer */
#define EMAC_MAX_PKT_SIZE  1536UL   /*!<  Number of HDR + EXTRA + VLAN_TAG + PAYLOAD + CRC \hideinitializer */

#define EMAC_LINK_DOWN    0UL       /*!<  Ethernet link is down \hideinitializer */
#define EMAC_LINK_100F    1UL       /*!<  Ethernet link is 100Mbps full duplex \hideinitializer */
#define EMAC_LINK_100H    2UL       /*!<  Ethernet link is 100Mbps half duplex \hideinitializer */
#define EMAC_LINK_10F     3UL       /*!<  Ethernet link is 10Mbps full duplex \hideinitializer */
#define EMAC_LINK_10H     4UL       /*!<  Ethernet link is 10Mbps half duplex \hideinitializer */

/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */

/**
    @addtogroup EMAC_CONST EMAC Bit Field Definition
    Constant Definitions for EMAC Controller
@{ */

#define EMAC_CAMCMR_AUP_Pos              (0)                                               /*!< EMAC::CAMCMR: AUP Position           */
#define EMAC_CAMCMR_AUP_Msk              (0x1ul << EMAC_CAMCMR_AUP_Pos)                    /*!< EMAC::CAMCMR: AUP Mask               */

#define EMAC_CAMCMR_AMP_Pos              (1)                                               /*!< EMAC::CAMCMR: AMP Position           */
#define EMAC_CAMCMR_AMP_Msk              (0x1ul << EMAC_CAMCMR_AMP_Pos)                    /*!< EMAC::CAMCMR: AMP Mask               */

#define EMAC_CAMCMR_ABP_Pos              (2)                                               /*!< EMAC::CAMCMR: ABP Position           */
#define EMAC_CAMCMR_ABP_Msk              (0x1ul << EMAC_CAMCMR_ABP_Pos)                    /*!< EMAC::CAMCMR: ABP Mask               */

#define EMAC_CAMCMR_CCCAM_Pos            (3)                                               /*!< EMAC::CAMCMR: COMPEN Position        */
#define EMAC_CAMCMR_CCCAM_Msk            (0x1ul << EMAC_CAMCMR_CCCAM_Pos)                  /*!< EMAC::CAMCMR: COMPEN Mask            */

#define EMAC_CAMCMR_ECMP_Pos             (4)                                               /*!< EMAC::CAMCMR: ECMP Position         */
#define EMAC_CAMCMR_ECMP_Msk             (0x1ul << EMAC_CAMCMR_ECMP_Pos)                   /*!< EMAC::CAMCMR: ECMP Mask             */

#define EMAC_CAMEN_CAMxEN_Pos            (0)                                               /*!< EMAC::CAMEN: CAMxEN Position         */
#define EMAC_CAMEN_CAMxEN_Msk            (0x1ul << EMAC_CAMEN_CAMxEN_Pos)                  /*!< EMAC::CAMEN: CAMxEN Mask             */

#define EMAC_CAMxM_MACADDR2_Pos          (0)                                               /*!< EMAC::CAMxM: MACADDR2 Position       */
#define EMAC_CAMxM_MACADDR2_Msk          (0xfful << EMAC_CAMxM_MACADDR2_Pos)               /*!< EMAC::CAMxM: MACADDR2 Mask           */

#define EMAC_CAMxM_MACADDR3_Pos          (8)                                               /*!< EMAC::CAMxM: MACADDR3 Position       */
#define EMAC_CAMxM_MACADDR3_Msk          (0xfful << EMAC_CAMxM_MACADDR3_Pos)               /*!< EMAC::CAMxM: MACADDR3 Mask           */

#define EMAC_CAMxM_MACADDR4_Pos          (16)                                              /*!< EMAC::CAMxM: MACADDR4 Position       */
#define EMAC_CAMxM_MACADDR4_Msk          (0xfful << EMAC_CAMxM_MACADDR4_Pos)               /*!< EMAC::CAMxM: MACADDR4 Mask           */

#define EMAC_CAMxM_MACADDR5_Pos          (24)                                              /*!< EMAC::CAMxM: MACADDR5 Position       */
#define EMAC_CAMxM_MACADDR5_Msk          (0xfful << EMAC_CAMxM_MACADDR5_Pos)               /*!< EMAC::CAMxM: MACADDR5 Mask           */

#define EMAC_CAMxL_MACADDR0_Pos          (16)                                              /*!< EMAC::CAMxL: MACADDR0 Position       */
#define EMAC_CAMxL_MACADDR0_Msk          (0xfful << EMAC_CAMxL_MACADDR0_Pos)               /*!< EMAC::CAMxL: MACADDR0 Mask           */

#define EMAC_CAMxL_MACADDR1_Pos          (24)                                              /*!< EMAC::CAMxL: MACADDR1 Position       */
#define EMAC_CAMxL_MACADDR1_Msk          (0xfful << EMAC_CAMxL_MACADDR1_Pos)               /*!< EMAC::CAMxL: MACADDR1 Mask           */

#define EMAC_CAM15MSB_OPCODE_Pos         (0)                                               /*!< EMAC::CAM15MSB: OPCODE Position      */
#define EMAC_CAM15MSB_OPCODE_Msk         (0xfffful << EMAC_CAM15MSB_OPCODE_Pos)            /*!< EMAC::CAM15MSB: OPCODE Mask          */

#define EMAC_CAM15MSB_LENGTH_Pos         (16)                                              /*!< EMAC::CAM15MSB: LENGTH Position      */
#define EMAC_CAM15MSB_LENGTH_Msk         (0xfffful << EMAC_CAM15MSB_LENGTH_Pos)            /*!< EMAC::CAM15MSB: LENGTH Mask          */

#define EMAC_CAM15LSB_OPERAND_Pos        (24)                                              /*!< EMAC::CAM15LSB: OPERAND Position     */
#define EMAC_CAM15LSB_OPERAND_Msk        (0xfful << EMAC_CAM15LSB_OPERAND_Pos)             /*!< EMAC::CAM15LSB: OPERAND Mask         */

#define EMAC_TXDLSA_TXDSA_Pos            (0)                                               /*!< EMAC::TXDLSA: TXDSA Position          */
#define EMAC_TXDLSA_TXDSA_Msk            (0xfffffffful << EMAC_TXDLSA_TXDSA_Pos)           /*!< EMAC::TXDLSA: TXDSA Mask              */

#define EMAC_RXDLSA_RXDSA_Pos            (0)                                               /*!< EMAC::RXDLSA: RXDSA Position          */
#define EMAC_RXDSA_RXDSA_Msk             (0xfffffffful << EMAC_RXDLSA_RXDSA_Pos)           /*!< EMAC::RXDLSA: RXDSA Mask              */

#define EMAC_MCMDR_RXON_Pos              (0)                                               /*!< EMAC::MCMDR: RXON Position             */
#define EMAC_MCMDR_RXON_Msk              (0x1ul << EMAC_MCMDR_RXON_Pos)                    /*!< EMAC::MCMDR: RXON Mask                 */

#define EMAC_MCMDR_ALP_Pos               (1)                                               /*!< EMAC::MCMDR: ALP Position              */
#define EMAC_MCMDR_ALP_Msk               (0x1ul << EMAC_MCMDR_ALP_Pos)                     /*!< EMAC::MCMDR: ALP Mask                  */

#define EMAC_MCMDR_ARP_Pos               (2)                                               /*!< EMAC::MCMDR: ARP Position              */
#define EMAC_MCMDR_ARP_Msk               (0x1ul << EMAC_MCMDR_ARP_Pos)                     /*!< EMAC::MCMDR: ARP Mask                  */

#define EMAC_MCMDR_ACP_Pos               (3)                                               /*!< EMAC::MCMDR: ACP Position              */
#define EMAC_MCMDR_ACP_Msk               (0x1ul << EMAC_MCMDR_ACP_Pos)                     /*!< EMAC::MCMDR: ACP Mask                  */

#define EMAC_MCMDR_AEP_Pos               (4)                                               /*!< EMAC::MCMDR: AEP Position              */
#define EMAC_MCMDR_AEP_Msk               (0x1ul << EMAC_MCMDR_AEP_Pos)                     /*!< EMAC::MCMDR: AEP Mask                  */

#define EMAC_MCMDR_STRIPCRC_Pos          (5)                                               /*!< EMAC::MCMDR: STRIPCRC Position         */
#define EMAC_MCMDR_STRIPCRC_Msk          (0x1ul << EMAC_MCMDR_STRIPCRC_Pos)                /*!< EMAC::MCMDR: STRIPCRC Mask             */

#define EMAC_MCMDR_WOLEN_Pos             (6)                                               /*!< EMAC::MCMDR: WOLEN Position            */
#define EMAC_MCMDR_WOLEN_Msk             (0x1ul << EMAC_MCMDR_WOLEN_Pos)                   /*!< EMAC::MCMDR: WOLEN Mask                */

#define EMAC_MCMDR_TXON_Pos              (8)                                               /*!< EMAC::MCMDR: TXON Position             */
#define EMAC_MCMDR_TXON_Msk              (0x1ul << EMAC_MCMDR_TXON_Pos)                    /*!< EMAC::MCMDR: TXON Mask                 */

#define EMAC_MCMDR_NODEF_Pos             (9)                                               /*!< EMAC::MCMDR: NODEF Position            */
#define EMAC_MCMDR_NODEF_Msk             (0x1ul << EMAC_MCMDR_NODEF_Pos)                   /*!< EMAC::MCMDR: NODEF Mask                */

#define EMAC_MCMDR_SDPZ_Pos              (16)                                              /*!< EMAC::MCMDR: SDPZ Position             */
#define EMAC_MCMDR_SDPZ_Msk              (0x1ul << EMAC_MCMDR_SDPZ_Pos)                    /*!< EMAC::MCMDR: SDPZ Mask                 */

#define EMAC_MCMDR_SQECHKEN_Pos          (17)                                              /*!< EMAC::MCMDR: SQECHKEN Position         */
#define EMAC_MCMDR_SQECHKEN_Msk          (0x1ul << EMAC_MCMDR_SQECHKEN_Pos)                /*!< EMAC::MCMDR: SQECHKEN Mask             */

#define EMAC_MCMDR_FUDUP_Pos             (18)                                              /*!< EMAC::MCMDR: FUDUP Position            */
#define EMAC_MCMDR_FUDUP_Msk             (0x1ul << EMAC_MCMDR_FUDUP_Pos)                   /*!< EMAC::MCMDR: FUDUP Mask                */

#define EMAC_MCMDR_RMIIRXCTL_Pos         (19)                                              /*!< EMAC::MCMDR: RMIIRXCTL Position        */
#define EMAC_MCMDR_RMIIRXCTL_Msk         (0x1ul << EMAC_MCMDR_RMIIRXCTL_Pos)               /*!< EMAC::MCMDR: RMIIRXCTL Mask            */

#define EMAC_MCMDR_OPMODE_Pos            (20)                                              /*!< EMAC::MCMDR: OPMODE Position           */
#define EMAC_MCMDR_OPMODE_Msk            (0x1ul << EMAC_MCMDR_OPMODE_Pos)                  /*!< EMAC::MCMDR: OPMODE Mask               */

#define EMAC_MCMDR_RMIIEN_Pos            (22)                                              /*!< EMAC::MCMDR: RMIIEN Position           */
#define EMAC_MCMDR_RMIIEN_Msk            (0x1ul << EMAC_MCMDR_RMIIEN_Pos)                  /*!< EMAC::MCMDR: RMIIEN Mask               */

#define EMAC_MCMDR_RST_Pos               (24)                                              /*!< EMAC::MCMDR: RST Position              */
#define EMAC_MCMDR_RST_Msk               (0x1ul << EMAC_MCMDR_RST_Pos)                     /*!< EMAC::MCMDR: RST Mask                  */

#define EMAC_MIID_DATA_Pos               (0)                                               /*!< EMAC::MIID: DATA Position         */
#define EMAC_MIID_DATA_Msk               (0xfffful << EMAC_MIID_DATA_Pos)                  /*!< EMAC::MIID: DATA Mask             */

#define EMAC_MIIDA_PHYRAD_Pos            (0)                                               /*!< EMAC::MIIDA: PHYRAD Position       */
#define EMAC_MIIDA_PHYRAD_Msk            (0x1ful << EMAC_MIIDA_PHYRAD_Pos)                 /*!< EMAC::MIIDA: PHYRAD Mask           */

#define EMAC_MIIDA_PHYAD_Pos             (8)                                               /*!< EMAC::MIIDA: PHYAD Position      */
#define EMAC_MIIDA_PHYAD_Msk             (0x1ful << EMAC_MIIDA_PHYAD_Pos)                  /*!< EMAC::MIIDA: PHYAD Mask          */

#define EMAC_MIIDA_WRITE_Pos             (16)                                              /*!< EMAC::MIIDA: WRITE Position        */
#define EMAC_MIIDA_WRITE_Msk             (0x1ul << EMAC_MIIDA_WRITE_Pos)                   /*!< EMAC::MIIDA: WRITE Mask            */

#define EMAC_MIIDA_BUSY_Pos              (17)                                              /*!< EMAC::MIIDA: BUSY Position         */
#define EMAC_MIIDA_BUSY_Msk              (0x1ul << EMAC_MIIDA_BUSY_Pos)                    /*!< EMAC::MIIDA: BUSY Mask             */

#define EMAC_MIIDA_PREAMSP_Pos           (18)                                              /*!< EMAC::MIIDA: PREAMSP Position      */
#define EMAC_MIIDA_PREAMSP_Msk           (0x1ul << EMAC_MIIDA_PREAMSP_Pos)                 /*!< EMAC::MIIDA: PREAMSP Mask          */

#define EMAC_MIIDA_MDCON_Pos             (19)                                              /*!< EMAC::MIIDA: MDCON Position        */
#define EMAC_MIIDA_MDCON_Msk             (0x1ul << EMAC_MIIDA_MDCON_Pos)                   /*!< EMAC::MIIDA: MDCON Mask            */

#define EMAC_FFTCR_RXTHD_Pos             (0)                                               /*!< EMAC::FFTCR: RXTHD Position     */
#define EMAC_FFTCR_RXTHD_Msk             (0x3ul << EMAC_FFTCR_RXTHD_Pos)                   /*!< EMAC::FFTCR: RXTHD Mask         */

#define EMAC_FFTCR_TXTHD_Pos             (8)                                               /*!< EMAC::FFTCR: TXTHD Position     */
#define EMAC_FFTCR_TXTHD_Msk             (0x3ul << EMAC_FFTCR_TXTHD_Pos)                   /*!< EMAC::FFTCR: TXTHD Mask         */

#define EMAC_FFTCR_BURSTLEN_Pos          (20)                                              /*!< EMAC::FFTCR: BURSTLEN Position     */
#define EMAC_FFTCR_BURSTLEN_Msk          (0x3ul << EMAC_FFTCR_BURSTLEN_Pos)                /*!< EMAC::FFTCR: BURSTLEN Mask         */

#define EMAC_TSDR_TSD_Pos                (0)                                               /*!< EMAC::TSDR: TSD Position            */
#define EMAC_TSDR_TSD_Msk                (0xfffffffful << EMAC_TSDR_TSD_Pos)               /*!< EMAC::TSDR: TSD Mask                */

#define EMAC_RSDR_RSD_Pos                (0)                                               /*!< EMAC::RSDR: RSD Position            */
#define EMAC_RSDR_RSD_Msk                (0xfffffffful << EMAC_RSDR_RSD_Pos)               /*!< EMAC::RSDR: RSD Mask                */

#define EMAC_DMARFC_RXMS_Pos             (0)                                               /*!< EMAC::DMARFC: RXMS Position            */
#define EMAC_DMARFC_RXMS_Msk             (0xfffful << EMAC_DMARFC_RXMS_Pos)                /*!< EMAC::DMARFC: RXMS Mask                */

#define EMAC_MIEN_RXIEN_Pos              (0)                                               /*!< EMAC::MIEN: RXIEN Position          */
#define EMAC_MIEN_RXIEN_Msk              (0x1ul << EMAC_MIEN_RXIEN_Pos)                    /*!< EMAC::MIEN: RXIEN Mask              */

#define EMAC_MIEN_CRCEIEN_Pos            (1)                                               /*!< EMAC::MIEN: CRCEIEN Position        */
#define EMAC_MIEN_CRCEIEN_Msk            (0x1ul << EMAC_MIEN_CRCEIEN_Pos)                  /*!< EMAC::MIEN: CRCEIEN Mask            */

#define EMAC_MIEN_RXOVIEN_Pos            (2)                                               /*!< EMAC::MIEN: RXOVIEN Position        */
#define EMAC_MIEN_RXOVIEN_Msk            (0x1ul << EMAC_MIEN_RXOVIEN_Pos)                  /*!< EMAC::MIEN: RXOVIEN Mask            */

#define EMAC_MIEN_LPIEN_Pos              (3)                                               /*!< EMAC::MIEN: LPIEN Position          */
#define EMAC_MIEN_LPIEN_Msk              (0x1ul << EMAC_MIEN_LPIEN_Pos)                    /*!< EMAC::MIEN: LPIEN Mask              */

#define EMAC_MIEN_RXGDIEN_Pos            (4)                                               /*!< EMAC::MIEN: RXGDIEN Position        */
#define EMAC_MIEN_RXGDIEN_Msk            (0x1ul << EMAC_MIEN_RXGDIEN_Pos)                  /*!< EMAC::MIEN: RXGDIEN Mask            */

#define EMAC_MIEN_ALIEIEN_Pos            (5)                                               /*!< EMAC::MIEN: ALIEIEN Position        */
#define EMAC_MIEN_ALIEIEN_Msk            (0x1ul << EMAC_MIEN_ALIEIEN_Pos)                  /*!< EMAC::MIEN: ALIEIEN Mask            */

#define EMAC_MIEN_RPIEN_Pos              (6)                                               /*!< EMAC::MIEN: RPIEN Position          */
#define EMAC_MIEN_RPIEN_Msk              (0x1ul << EMAC_MIEN_RPIEN_Pos)                    /*!< EMAC::MIEN: RPIEN Mask              */

#define EMAC_MIEN_MMPIEN_Pos             (7)                                               /*!< EMAC::MIEN: MMPIEN Position       */
#define EMAC_MIEN_MMPIEN_Msk             (0x1ul << EMAC_MIEN_MMPIEN_Pos)                   /*!< EMAC::MIEN: MMPIEN Mask           */

#define EMAC_MIEN_MFLEIEN_Pos            (8)                                               /*!< EMAC::MIEN: MFLEIEN Position        */
#define EMAC_MIEN_MFLEIEN_Msk            (0x1ul << EMAC_MIEN_MFLEIEN_Pos)                  /*!< EMAC::MIEN: MFLEIEN Mask            */

#define EMAC_MIEN_DENIEN_Pos             (9)                                               /*!< EMAC::MIEN: DENIEN Position         */
#define EMAC_MIEN_DENIEN_Msk             (0x1ul << EMAC_MIEN_DENIEN_Pos)                   /*!< EMAC::MIEN: DENIEN Mask             */

#define EMAC_MIEN_RDUIEN_Pos             (10)                                              /*!< EMAC::MIEN: RDUIEN Position         */
#define EMAC_MIEN_RDUIEN_Msk             (0x1ul << EMAC_MIEN_RDUIEN_Pos)                   /*!< EMAC::MIEN: RDUIEN Mask             */

#define EMAC_MIEN_RXBEIEN_Pos            (11)                                              /*!< EMAC::MIEN: RXBEIEN Position        */
#define EMAC_MIEN_RXBEIEN_Msk            (0x1ul << EMAC_MIEN_RXBEIEN_Pos)                  /*!< EMAC::MIEN: RXBEIEN Mask            */

#define EMAC_MIEN_CFRIEN_Pos             (14)                                              /*!< EMAC::MIEN: CFRIEN Position         */
#define EMAC_MIEN_CFRIEN_Msk             (0x1ul << EMAC_MIEN_CFRIEN_Pos)                   /*!< EMAC::MIEN: CFRIEN Mask             */

#define EMAC_MIEN_WOLIEN_Pos             (15)                                              /*!< EMAC::MIEN: WOLIEN Position         */
#define EMAC_MIEN_WOLIEN_Msk             (0x1ul << EMAC_MIEN_WOLIEN_Pos)                   /*!< EMAC::MIEN: WOLIEN Mask             */

#define EMAC_MIEN_TXIEN_Pos              (16)                                              /*!< EMAC::MIEN: TXIEN Position          */
#define EMAC_MIEN_TXIEN_Msk              (0x1ul << EMAC_MIEN_TXIEN_Pos)                    /*!< EMAC::MIEN: TXIEN Mask              */

#define EMAC_MIEN_TXUDIEN_Pos            (17)                                              /*!< EMAC::MIEN: TXUDIEN Position        */
#define EMAC_MIEN_TXUDIEN_Msk            (0x1ul << EMAC_MIEN_TXUDIEN_Pos)                  /*!< EMAC::MIEN: TXUDIEN Mask            */

#define EMAC_MIEN_TXCPIEN_Pos            (18)                                              /*!< EMAC::MIEN: TXCPIEN Position        */
#define EMAC_MIEN_TXCPIEN_Msk            (0x1ul << EMAC_MIEN_TXCPIEN_Pos)                  /*!< EMAC::MIEN: TXCPIEN Mask            */

#define EMAC_MIEN_EXDEFIEN_Pos           (19)                                              /*!< EMAC::MIEN: EXDEFIEN Position       */
#define EMAC_MIEN_EXDEFIEN_Msk           (0x1ul << EMAC_MIEN_EXDEFIEN_Pos)                 /*!< EMAC::MIEN: EXDEFIEN Mask           */

#define EMAC_MIEN_NCSIEN_Pos             (20)                                              /*!< EMAC::MIEN: NCSIEN Position         */
#define EMAC_MIEN_NCSIEN_Msk             (0x1ul << EMAC_MIEN_NCSIEN_Pos)                   /*!< EMAC::MIEN: NCSIEN Mask             */

#define EMAC_MIEN_TXABTIEN_Pos           (21)                                              /*!< EMAC::MIEN: TXABTIEN Position       */
#define EMAC_MIEN_TXABTIEN_Msk           (0x1ul << EMAC_MIEN_TXABTIEN_Pos)                 /*!< EMAC::MIEN: TXABTIEN Mask           */

#define EMAC_MIEN_LCIEN_Pos              (22)                                              /*!< EMAC::MIEN: LCIEN Position          */
#define EMAC_MIEN_LCIEN_Msk              (0x1ul << EMAC_MIEN_LCIEN_Pos)                    /*!< EMAC::MIEN: LCIEN Mask              */

#define EMAC_MIEN_TDUIEN_Pos             (23)                                              /*!< EMAC::MIEN: TDUIEN Position         */
#define EMAC_MIEN_TDUIEN_Msk             (0x1ul << EMAC_MIEN_TDUIEN_Pos)                   /*!< EMAC::MIEN: TDUIEN Mask             */

#define EMAC_MIEN_TXBEIEN_Pos            (24)                                              /*!< EMAC::MIEN: TXBEIEN Position        */
#define EMAC_MIEN_TXBEIEN_Msk            (0x1ul << EMAC_MIEN_TXBEIEN_Pos)                  /*!< EMAC::MIEN: TXBEIEN Mask            */

#define EMAC_MIEN_TSALMIEN_Pos           (28)                                              /*!< EMAC::MIEN: TSALMIEN Position       */
#define EMAC_MIEN_TSALMIEN_Msk           (0x1ul << EMAC_MIEN_TSALMIEN_Pos)                 /*!< EMAC::MIEN: TSALMIEN Mask           */

#define EMAC_MISTA_RXIF_Pos              (0)                                               /*!< EMAC::MISTA: RXIF Position          */
#define EMAC_MISTA_RXIF_Msk              (0x1ul << EMAC_MISTA_RXIF_Pos)                    /*!< EMAC::MISTA: RXIF Mask              */

#define EMAC_MISTA_CRCEIF_Pos            (1)                                               /*!< EMAC::MISTA: CRCEIF Position        */
#define EMAC_MISTA_CRCEIF_Msk            (0x1ul << EMAC_MISTA_CRCEIF_Pos)                  /*!< EMAC::MISTA: CRCEIF Mask            */

#define EMAC_MISTA_RXOVIF_Pos            (2)                                               /*!< EMAC::MISTA: RXOVIF Position        */
#define EMAC_MISTA_RXOVIF_Msk            (0x1ul << EMAC_MISTA_RXOVIF_Pos)                  /*!< EMAC::MISTA: RXOVIF Mask            */

#define EMAC_MISTA_LPIF_Pos              (3)                                               /*!< EMAC::MISTA: LPIF Position          */
#define EMAC_MISTA_LPIF_Msk              (0x1ul << EMAC_MISTA_LPIF_Pos)                    /*!< EMAC::MISTA: LPIF Mask              */

#define EMAC_MISTA_RXGDIF_Pos            (4)                                               /*!< EMAC::MISTA: RXGDIF Position        */
#define EMAC_MISTA_RXGDIF_Msk            (0x1ul << EMAC_MISTA_RXGDIF_Pos)                  /*!< EMAC::MISTA: RXGDIF Mask            */

#define EMAC_MISTA_ALIEIF_Pos            (5)                                               /*!< EMAC::MISTA: ALIEIF Position        */
#define EMAC_MISTA_ALIEIF_Msk            (0x1ul << EMAC_MISTA_ALIEIF_Pos)                  /*!< EMAC::MISTA: ALIEIF Mask            */

#define EMAC_MISTA_RPIF_Pos              (6)                                               /*!< EMAC::MISTA: RPIF Position          */
#define EMAC_MISTA_RPIF_Msk              (0x1ul << EMAC_MISTA_RPIF_Pos)                    /*!< EMAC::MISTA: RPIF Mask              */

#define EMAC_MISTA_MPCOVIF_Pos           (7)                                               /*!< EMAC::MISTA: MPCOVIF Position       */
#define EMAC_MISTA_MPCOVIF_Msk           (0x1ul << EMAC_MISTA_MPCOVIF_Pos)                 /*!< EMAC::MISTA: MPCOVIF Mask           */

#define EMAC_MISTA_MFLEIF_Pos            (8)                                               /*!< EMAC::MISTA: MFLEIF Position        */
#define EMAC_MISTA_MFLEIF_Msk            (0x1ul << EMAC_MISTA_MFLEIF_Pos)                 /*!< EMAC::MISTA: MFLEIF Mask            */

#define EMAC_MISTA_DENIF_Pos             (9)                                               /*!< EMAC::MISTA: DENIF Position         */
#define EMAC_MISTA_DENIF_Msk             (0x1ul << EMAC_MISTA_DENIF_Pos)                   /*!< EMAC::MISTA: DENIF Mask             */

#define EMAC_MISTA_RDUIF_Pos             (10)                                              /*!< EMAC::MISTA: RDUIF Position         */
#define EMAC_MISTA_RDUIF_Msk             (0x1ul << EMAC_MISTA_RDUIF_Pos)                   /*!< EMAC::MISTA: RDUIF Mask             */

#define EMAC_MISTA_RXBEIF_Pos            (11)                                              /*!< EMAC::MISTA: RXBEIF Position        */
#define EMAC_MISTA_RXBEIF_Msk            (0x1ul << EMAC_MISTA_RXBEIF_Pos)                  /*!< EMAC::MISTA: RXBEIF Mask            */

#define EMAC_MISTA_CFRIF_Pos             (14)                                              /*!< EMAC::MISTA: CFRIF Position         */
#define EMAC_MISTA_CFRIF_Msk             (0x1ul << EMAC_MISTA_CFRIF_Pos)                   /*!< EMAC::MISTA: CFRIF Mask             */

#define EMAC_MISTA_WOLIF_Pos             (15)                                              /*!< EMAC::MISTA: WOLIF Position         */
#define EMAC_MISTA_WOLIF_Msk             (0x1ul << EMAC_MISTA_WOLIF_Pos)                   /*!< EMAC::MISTA: WOLIF Mask             */

#define EMAC_MISTA_TXIF_Pos              (16)                                              /*!< EMAC::MISTA: TXIF Position          */
#define EMAC_MISTA_TXIF_Msk              (0x1ul << EMAC_MISTA_TXIF_Pos)                    /*!< EMAC::MISTA: TXIF Mask              */

#define EMAC_MISTA_TXUDIF_Pos            (17)                                              /*!< EMAC::MISTA: TXUDIF Position        */
#define EMAC_MISTA_TXUDIF_Msk            (0x1ul << EMAC_MISTA_TXUDIF_Pos)                  /*!< EMAC::MISTA: TXUDIF Mask            */

#define EMAC_MISTA_TXCPIF_Pos            (18)                                              /*!< EMAC::MISTA: TXCPIF Position        */
#define EMAC_MISTA_TXCPIF_Msk            (0x1ul << EMAC_MISTA_TXCPIF_Pos)                  /*!< EMAC::MISTA: TXCPIF Mask            */

#define EMAC_MISTA_EXDEFIF_Pos           (19)                                              /*!< EMAC::MISTA: EXDEFIF Position       */
#define EMAC_MISTA_EXDEFIF_Msk           (0x1ul << EMAC_MISTA_EXDEFIF_Pos)                 /*!< EMAC::MISTA: EXDEFIF Mask           */

#define EMAC_MISTA_NCSIF_Pos             (20)                                              /*!< EMAC::MISTA: NCSIF Position         */
#define EMAC_MISTA_NCSIF_Msk             (0x1ul << EMAC_MISTA_NCSIF_Pos)                   /*!< EMAC::MISTA: NCSIF Mask             */

#define EMAC_MISTA_TXABTIF_Pos           (21)                                              /*!< EMAC::MISTA: TXABTIF Position       */
#define EMAC_MISTA_TXABTIF_Msk           (0x1ul << EMAC_MISTA_TXABTIF_Pos)                 /*!< EMAC::MISTA: TXABTIF Mask           */

#define EMAC_MISTA_LCIF_Pos              (22)                                              /*!< EMAC::MISTA: LCIF Position          */
#define EMAC_MISTA_LCIF_Msk              (0x1ul << EMAC_MISTA_LCIF_Pos)                    /*!< EMAC::MISTA: LCIF Mask              */

#define EMAC_MISTA_TDUIF_Pos             (23)                                              /*!< EMAC::MISTA: TDUIF Position         */
#define EMAC_MISTA_TDUIF_Msk             (0x1ul << EMAC_MISTA_TDUIF_Pos)                   /*!< EMAC::MISTA: TDUIF Mask             */

#define EMAC_MISTA_TXBEIF_Pos            (24)                                              /*!< EMAC::MISTA: TXBEIF Position        */
#define EMAC_MISTA_TXBEIF_Msk            (0x1ul << EMAC_MISTA_TXBEIF_Pos)                  /*!< EMAC::MISTA: TXBEIF Mask            */

#define EMAC_MISTA_TSALMIF_Pos           (28)                                              /*!< EMAC::MISTA: TSALMIF Position       */
#define EMAC_MISTA_TSALMIF_Msk           (0x1ul << EMAC_MISTA_TSALMIF_Pos)                 /*!< EMAC::MISTA: TSALMIF Mask           */

#define EMAC_MGSTA_CFR_Pos               (0)                                               /*!< EMAC::MGSTA: CFR Position           */
#define EMAC_MGSTA_CFR_Msk               (0x1ul << EMAC_MGSTA_CFR_Pos)                     /*!< EMAC::MGSTA: CFR Mask               */

#define EMAC_MGSTA_RXHALT_Pos            (1)                                               /*!< EMAC::MGSTA: RXHALT Position        */
#define EMAC_MGSTA_RXHALT_Msk            (0x1ul << EMAC_MGSTA_RXHALT_Pos)                  /*!< EMAC::MGSTA: RXHALT Mask            */

#define EMAC_MGSTA_RXFFULL_Pos           (2)                                               /*!< EMAC::MGSTA: RXFFULL Position       */
#define EMAC_MGSTA_RXFFULL_Msk           (0x1ul << EMAC_MGSTA_RXFFULL_Pos)                 /*!< EMAC::MGSTA: RXFFULL Mask           */

#define EMAC_MGSTA_COLCNT_Pos            (4)                                               /*!< EMAC::MGSTA: COLCNT Position        */
#define EMAC_MGSTA_COLCNT_Msk            (0xful << EMAC_MGSTA_COLCNT_Pos)                  /*!< EMAC::MGSTA: COLCNT Mask            */

#define EMAC_MGSTA_DEF_Pos               (8)                                               /*!< EMAC::MGSTA: DEF Position           */
#define EMAC_MGSTA_DEF_Msk               (0x1ul << EMAC_MGSTA_DEF_Pos)                     /*!< EMAC::MGSTA: DEF Mask               */

#define EMAC_MGSTA_TXPAUSED_Pos          (9)                                               /*!< EMAC::MGSTA: TXPAUSED Position      */
#define EMAC_MGSTA_TXPAUSED_Msk          (0x1ul << EMAC_MGSTA_TXPAUSED_Pos)                /*!< EMAC::MGSTA: TXPAUSED Mask          */

#define EMAC_MGSTA_SQE_Pos               (10)                                              /*!< EMAC::MGSTA: SQE Position           */
#define EMAC_MGSTA_SQE_Msk               (0x1ul << EMAC_MGSTA_SQE_Pos)                     /*!< EMAC::MGSTA: SQE Mask               */

#define EMAC_MGSTA_TXHALT_Pos            (11)                                              /*!< EMAC::MGSTA: TXHALT Position        */
#define EMAC_MGSTA_TXHALT_Msk            (0x1ul << EMAC_MGSTA_TXHALT_Pos)                  /*!< EMAC::MGSTA: TXHALT Mask            */

#define EMAC_MGSTA_RPSTS_Pos             (12)                                              /*!< EMAC::MGSTA: RPSTS Position         */
#define EMAC_MGSTA_RPSTS_Msk             (0x1ul << EMAC_MGSTA_RPSTS_Pos)                   /*!< EMAC::MGSTA: RPSTS Mask             */

#define EMAC_MPCNT_MPC_Pos               (0)                                               /*!< EMAC::MPCNT: MPC Position          */
#define EMAC_MPCNT_MPC_Msk               (0xfffful << EMAC_MPCNT_MPC_Pos)                  /*!< EMAC::MPCNT: MPC Mask              */

#define EMAC_MRPC_MRPC_Pos               (0)                                               /*!< EMAC::MRPC: MRPC Position          */
#define EMAC_MRPC_MRPC_Msk               (0xfffful << EMAC_MRPC_MRPC_Pos)                  /*!< EMAC::MRPC: MRPC Mask              */

#define EMAC_DMARFS_RXFLT_Pos            (0)                                               /*!< EMAC::DMARFS: RXFLT Position          */
#define EMAC_DMARFS_RXFLT_Msk            (0xfffful << EMAC_DMARFS_RXFLT_Pos)               /*!< EMAC::DMARFS: RXFLT Mask              */

#define EMAC_CTXDSA_CTXDSA_Pos           (0)                                               /*!< EMAC::CTXDSA: CTXDSA Position        */
#define EMAC_CTXDSA_CTXDSA_Msk           (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos)          /*!< EMAC::CTXDSA: CTXDSA Mask            */

#define EMAC_CTXBSA_CTXBSA_Pos           (0)                                               /*!< EMAC::CTXBSA: CTXBSA Position        */
#define EMAC_CTXBSA_CTXBSA_Msk           (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos)          /*!< EMAC::CTXBSA: CTXBSA Mask            */

#define EMAC_CRXDSA_CRXDSA_Pos           (0)                                               /*!< EMAC::CRXDSA: CRXDSA Position        */
#define EMAC_CRXDSA_CRXDSA_Msk           (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos)          /*!< EMAC::CRXDSA: CRXDSA Mask            */

#define EMAC_CRXBSA_CRXBSA_Pos           (0)                                               /*!< EMAC::CRXBSA: CRXBSA Position        */
#define EMAC_CRXBSA_CRXBSA_Msk           (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos)          /*!< EMAC::CRXBSA: CRXBSA Mask            */

#define EMAC_TSCTL_TSEN_Pos              (0)                                               /*!< EMAC::TSCTL: TSEN Position           */
#define EMAC_TSCTL_TSEN_Msk              (0x1ul << EMAC_TSCTL_TSEN_Pos)                    /*!< EMAC::TSCTL: TSEN Mask               */

#define EMAC_TSCTL_TSIEN_Pos             (1)                                               /*!< EMAC::TSCTL: TSIEN Position          */
#define EMAC_TSCTL_TSIEN_Msk             (0x1ul << EMAC_TSCTL_TSIEN_Pos)                   /*!< EMAC::TSCTL: TSIEN Mask              */

#define EMAC_TSCTL_TSMODE_Pos            (2)                                               /*!< EMAC::TSCTL: TSMODE Position         */
#define EMAC_TSCTL_TSMODE_Msk            (0x1ul << EMAC_TSCTL_TSMODE_Pos)                  /*!< EMAC::TSCTL: TSMODE Mask             */

#define EMAC_TSCTL_TSUPDATE_Pos          (3)                                               /*!< EMAC::TSCTL: TSUPDATE Position       */
#define EMAC_TSCTL_TSUPDATE_Msk          (0x1ul << EMAC_TSCTL_TSUPDATE_Pos)                /*!< EMAC::TSCTL: TSUPDATE Mask           */

#define EMAC_TSCTL_TSALMEN_Pos           (5)                                               /*!< EMAC::TSCTL: TSALMEN Position        */
#define EMAC_TSCTL_TSALMEN_Msk           (0x1ul << EMAC_TSCTL_TSALMEN_Pos)                 /*!< EMAC::TSCTL: TSALMEN Mask            */

#define EMAC_TSSEC_SEC_Pos               (0)                                               /*!< EMAC::TSSEC: SEC Position            */
#define EMAC_TSSEC_SEC_Msk               (0xfffffffful << EMAC_TSSEC_SEC_Pos)              /*!< EMAC::TSSEC: SEC Mask                */

#define EMAC_TSSUBSEC_SUBSEC_Pos         (0)                                               /*!< EMAC::TSSUBSEC: SUBSEC Position      */
#define EMAC_TSSUBSEC_SUBSEC_Msk         (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos)        /*!< EMAC::TSSUBSEC: SUBSEC Mask          */

#define EMAC_TSINC_CNTINC_Pos            (0)                                               /*!< EMAC::TSINC: CNTINC Position         */
#define EMAC_TSINC_CNTINC_Msk            (0xfful << EMAC_TSINC_CNTINC_Pos)                 /*!< EMAC::TSINC: CNTINC Mask             */

#define EMAC_TSADDEND_ADDEND_Pos         (0)                                               /*!< EMAC::TSADDEND: ADDEND Position      */
#define EMAC_TSADDEND_ADDEND_Msk         (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos)        /*!< EMAC::TSADDEND: ADDEND Mask          */

#define EMAC_TSUPDSEC_SEC_Pos            (0)                                               /*!< EMAC::TSUPDSEC: SEC Position           */
#define EMAC_TSUPDSEC_SEC_Msk            (0xfffffffful << EMAC_TSUPDSEC_SEC_Pos)           /*!< EMAC::TSUPDSEC: SEC Mask               */

#define EMAC_TSUPDSUBSEC_SUBSEC_Pos      (0)                                               /*!< EMAC::TSUPDSUBSEC: SUBSEC Position     */
#define EMAC_TSUPDSUBSEC_SUBSEC_Msk      (0xfffffffful << EMAC_TSUPDSUBSEC_SUBSEC_Pos)     /*!< EMAC::TSUPDSUBSEC: SUBSEC Mask         */

#define EMAC_TSALMSEC_SEC_Pos            (0)                                               /*!< EMAC::TSALMSEC: SEC Position           */
#define EMAC_TSALMSEC_SEC_Msk            (0xfffffffful << EMAC_TSALMSEC_SEC_Pos)           /*!< EMAC::TSALMSEC: SEC Mask               */

#define EMAC_TSALMSUBSEC_SUBSEC_Pos      (0)                                               /*!< EMAC::TSALMSUBSEC: SUBSEC Position     */
#define EMAC_TSALMSUBSEC_SUBSEC_Msk      (0xfffffffful << EMAC_TSALMSUBSEC_SUBSEC_Pos)     /*!< EMAC::TSALMSUBSEC: SUBSEC Mask         */

/**@}*/ /* EMAC_CONST */

/**
    @addtogroup EMAC Ethernet MAC Controller(EMAC)
    Memory Mapped Structure for EMAC Controller
@{ */

typedef struct
{
    /**
     * @var EMAC_TypeDef::CAMCMR
     * Offset: 0x00  CAM Comparison Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |AUP       |Accept Unicast Packet
     * |        |          |The AUP controls the unicast packet reception
     * |        |          |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address.
     * |        |          |0 = EMAC receives packet depends on the CAM comparison result.
     * |        |          |1 = EMAC receives all unicast packets.
     * |[1]     |AMP       |Accept Multicast Packet
     * |        |          |The AMP controls the multicast packet reception
     * |        |          |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address.
     * |        |          |0 = EMAC receives packet depends on the CAM comparison result.
     * |        |          |1 = EMAC receives all multicast packets.
     * |[2]     |ABP       |Accept Broadcast Packet
     * |        |          |The ABP controls the broadcast packet reception
     * |        |          |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address.
     * |        |          |0 = EMAC receives packet depends on the CAM comparison result.
     * |        |          |1 = EMAC receives all broadcast packets.
     * |[3]     |COMPEN    |Complement CAM Comparison Enable Bit
     * |        |          |The COMPEN controls the complement of the CAM comparison result
     * |        |          |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address
     * |        |          |configured in CAM entry will be dropped
     * |        |          |And the incoming packet with destination MAC address does not configured in any CAM entry will be received.
     * |        |          |0 = Complement CAM comparison result Disabled.
     * |        |          |1 = Complement CAM comparison result Enabled.
     * |[4]     |CMPEN     |CAM Compare Enable Bit
     * |        |          |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition
     * |        |          |If software wants to receive a packet with specific destination MAC address, configures the MAC address
     * |        |          |into CAM 12~0, then enables that CAM entry and set CMPEN to 1.
     * |        |          |0 = CAM comparison function for destination MAC address recognition Disabled.
     * |        |          |1 = CAM comparison function for destination MAC address recognition Enabled.
     * @var EMAC_TypeDef::CAMEN
     * Offset: 0x04  CAM Enable Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |CAMxEN    |CAM Entry X Enable Bit
     * |        |          |The CAMxEN controls the validation of CAM entry x.
     * |        |          |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission
     * |        |          |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM
     * |        |          |entries all must be enabled first.
     * |        |          |0 = CAM entry x Disabled.
     * |        |          |1 = CAM entry x Enabled.
     * @var EMAC_TypeDef::CAMxM
     * Offset: 0x08 + (x)*0x8  CAMx Most Significant Word Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[7:0]   |MACADDR2  |MAC Address Byte 2
     * |[15:8]  |MACADDR3  |MAC Address Byte 3
     * |[23:16] |MACADDR4  |MAC Address Byte 4
     * |[31:24] |MACADDR5  |MAC Address Byte 5
     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
     * |        |          |The x can be the 0~14
     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAMxM is
     * |        |          |0x0050_BA33 and EMAC_CAMxL is 0xBA44_0000.
     * @var EMAC_TypeDef::CAMxL
     * Offset: 0x0C + (x)*0x8  CAMx Least Significant Word Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[23:16] |MACADDR0  |MAC Address Byte 0
     * |[31:24] |MACADDR1  |MAC Address Byte 1
     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
     * |        |          |The x can be the 0~14
     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAMxM is
     * |        |          |0x0050_BA33 and EMAC_CAMxL is 0xBA44_0000.
     * @var EMAC_TypeDef::CAM15MSB
     * Offset: 0x80  CAM15 Most Significant Word Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[15:0]  |OPCODE    |OP Code Field of PAUSE Control Frame
     * |        |          |In the PAUSE control frame, an op code field defined and is 0x0001.
     * |[31:16] |LENGTH    |LENGTH Field of PAUSE Control Frame
     * |        |          |In the PAUSE control frame, a LENGTH field defined and is 0x8808.
     * @var EMAC_TypeDef::CAM15LSB
     * Offset: 0x84  CAM15 Least Significant Word Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:24] |OPERAND   |Pause Parameter
     * |        |          |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination
     * |        |          |Ethernet MAC Controller paused
     * |        |          |The unit of the OPERAND is a slot time, the 512-bit time.
     * @var EMAC_TypeDef::TXDLSA
     * Offset: 0x88  Transmit Descriptor Link List Start Address Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |TXDSA     |Transmit Descriptor Link-list Start Address
     * |        |          |The TXDSA keeps the start address of transmit descriptor link-list
     * |        |          |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the
     * |        |          |current transmit descriptor start address register (EMAC_CTXDSA)
     * |        |          |The TXDSA does not be updated by EMAC
     * |        |          |During the operation, EMAC will ignore the bits [1:0] of TXDSA
     * |        |          |This means that TX descriptors must locate at word boundary memory address.
     * @var EMAC_TypeDef::RXDLSA
     * Offset: 0x8C  Receive Descriptor Link List Start Address Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |RXDSA     |Receive Descriptor Link-list Start Address
     * |        |          |The RXDSA keeps the start address of receive descriptor link-list
     * |        |          |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current
     * |        |          |receive descriptor start address register (EMAC_CRXDSA)
     * |        |          |The RXDSA does not be updated by EMAC
     * |        |          |During the operation, EMAC will ignore the bits [1:0] of RXDSA
     * |        |          |This means that RX descriptors must locate at word boundary memory address.
     * @var EMAC_TypeDef::MCMDR
     * Offset: 0x90  MAC Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |RXON      |Frame Reception ON
     * |        |          |The RXON controls the normal packet reception of EMAC
     * |        |          |If the RXON is set to high, the EMAC starts the packet reception process, including the RX
     * |        |          |descriptor fetching, packet reception and RX descriptor modification.
     * |        |          |It is necessary to finish EMAC initial sequence before enable RXON
     * |        |          |Otherwise, the EMAC operation is undefined.
     * |        |          |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet
     * |        |          |reception process after the current packet reception finished.
     * |        |          |0 = Packet reception process stopped.
     * |        |          |1 = Packet reception process started.
     * |[1]     |ALP       |Accept Long Packet
     * |        |          |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception
     * |        |          |If the ALP is set to high, the EMAC will accept the long packet.
     * |        |          |Otherwise, the long packet will be dropped.
     * |        |          |0 = Ethernet MAC controller dropped the long packet.
     * |        |          |1 = Ethernet MAC controller received the long packet.
     * |[2]     |ARP       |Accept Runt Packet
     * |        |          |The ARP controls the runt packet, which length is less than 64 bytes, reception
     * |        |          |If the ARP is set to high, the EMAC will accept the runt packet.
     * |        |          |Otherwise, the runt packet will be dropped.
     * |        |          |0 = Ethernet MAC controller dropped the runt packet.
     * |        |          |1 = Ethernet MAC controller received the runt packet.
     * |[3]     |ACP       |Accept Control Packet
     * |        |          |The ACP controls the control frame reception
     * |        |          |If the ACP is set to high, the EMAC will accept the control frame
     * |        |          |Otherwise, the control frame will be dropped
     * |        |          |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode.
     * |        |          |0 = Ethernet MAC controller dropped the control frame.
     * |        |          |1 = Ethernet MAC controller received the control frame.
     * |[4]     |AEP       |Accept CRC Error Packet
     * |        |          |The AEP controls the EMAC accepts or drops the CRC error packet
     * |        |          |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet.
     * |        |          |0 = Ethernet MAC controller dropped the CRC error packet.
     * |        |          |1 = Ethernet MAC controller received the CRC error packet.
     * |[5]     |STRIPCRC  |Strip CRC Checksum
     * |        |          |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum
     * |        |          |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet.
     * |        |          |0 = The 4 bytes CRC checksum is included in packet length calculation.
     * |        |          |1 = The 4 bytes CRC checksum is excluded in packet length calculation.
     * |[6]     |WOLEN     |Wake on LAN Enable Bit
     * |        |          |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet
     * |        |          |is Magic Packet and wakeup system from Power-down mode.
     * |        |          |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller
     * |        |          |would generate a wakeup event to wake system up from Power-down mode.
     * |        |          |0 = Wake-up by Magic Packet function Disabled.
     * |        |          |1 = Wake-up by Magic Packet function Enabled.
     * |[8]     |TXON      |Frame Transmission ON
     * |        |          |The TXON controls the normal packet transmission of EMAC
     * |        |          |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX
     * |        |          |descriptor fetching, packet transmission and TX descriptor modification.
     * |        |          |It is must to finish EMAC initial sequence before enable TXON
     * |        |          |Otherwise, the EMAC operation is undefined.
     * |        |          |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet
     * |        |          |transmission process after the current packet transmission finished.
     * |        |          |0 = Packet transmission process stopped.
     * |        |          |1 = Packet transmission process started.
     * |[9]     |NODEF     |No Deferral
     * |        |          |The NODEF controls the enable of deferral exceed counter
     * |        |          |If NODEF is set to high, the deferral exceed counter is disabled
     * |        |          |The NODEF is only useful while EMAC is operating on half duplex mode.
     * |        |          |0 = The deferral exceed counter Enabled.
     * |        |          |1 = The deferral exceed counter Disabled.
     * |[16]    |SDPZ      |Send PAUSE Frame
     * |        |          |The SDPZ controls the PAUSE control frame transmission.
     * |        |          |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured
     * |        |          |first and the corresponding CAM enable bit of CAMEN register also must be set.
     * |        |          |Then, set SDPZ to 1 enables the PAUSE control frame transmission.
     * |        |          |The SDPZ is a self-clear bit
     * |        |          |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically.
     * |        |          |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode.
     * |        |          |0 = PAUSE control frame transmission completed.
     * |        |          |1 = PAUSE control frame transmission Enabled.
     * |[17]    |SQECHKEN  |SQE Checking Enable Bit
     * |        |          |The SQECHKEN controls the enable of SQE checking
     * |        |          |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode
     * |        |          |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100Mbps
     * |        |          |or full duplex mode.
     * |        |          |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode.
     * |        |          |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode.
     * |[18]    |FUDUP     |Full Duplex Mode Selection
     * |        |          |The FUDUP controls that if EMAC is operating on full or half duplex mode.
     * |        |          |0 = EMAC operates in half duplex mode.
     * |        |          |1 = EMAC operates in full duplex mode.
     * |[19]    |RMIIRXCTL |RMII RX Control
     * |        |          |The RMIIRXCTL control the receive data sample in RMII mode
     * |        |          |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high.
     * |        |          |0 = RMII RX control disabled.
     * |        |          |1 = RMII RX control enabled.
     * |[20]    |OPMODE    |Operation Mode Selection
     * |        |          |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode
     * |        |          |The RST (EMAC_CTL[24]) would not affect OPMODE value.
     * |        |          |0 = EMAC operates in 10Mbps mode.
     * |        |          |1 = EMAC operates in 100Mbps mode.
     * |[22]    |RMIIEN    |RMII Mode Enable Bit
     * |        |          |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII
     * |        |          |interface or RMII interface
     * |        |          |The RST (EMAC_CTL[24]) would not affect RMIIEN value.
     * |        |          |0 = Ethernet MAC controller RMII mode Disabled.
     * |        |          |1 = Ethernet MAC controller RMII mode Enabled.
     * |        |          |NOTE: This field must keep 1.
     * |[24]    |RST       |Software Reset
     * |        |          |The RST implements a reset function to make the EMAC return default state
     * |        |          |The RST is a self-clear bit
     * |        |          |This means after the software reset finished, the RST will be cleared automatically
     * |        |          |Enable RST can also reset all control and status registers, exclusive of the control bits
     * |        |          |RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]).
     * |        |          |The EMAC re-initial is necessary after the software reset completed.
     * |        |          |0 = Software reset completed.
     * |        |          |1 = Software reset Enabled.
     * @var EMAC_TypeDef::MIID
     * Offset: 0x94  MII Management Data Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[15:0]  |DATA      |MII Management Data
     * |        |          |The DATA is the 16 bits data that will be written into the registers of external PHY for MII
     * |        |          |Management write command or the data from the registers of external PHY for MII Management read command.
     * @var EMAC_TypeDef::MIIDA
     * Offset: 0x98  MII Management Control and Address Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[4:0]   |PHYREG    |PHY Register Address
     * |        |          |The PHYREG keeps the address to indicate which register of external PHY is the target of the
     * |        |          |MII management command.
     * |[12:8]  |PHYADDR   |PHY Address
     * |        |          |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command.
     * |[16]    |WRITE     |Write Command
     * |        |          |The Write defines the MII management command is a read or write.
     * |        |          |0 = MII management command is a read command.
     * |        |          |1 = MII management command is a write command.
     * |[17]    |BUSY      |Busy Bit
     * |        |          |The BUSY controls the enable of the MII management frame generation
     * |        |          |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates
     * |        |          |the MII management frame to external PHY through MII Management I/F
     * |        |          |The BUSY is a self-clear bit
     * |        |          |This means the BUSY will be cleared automatically after the MII management command finished.
     * |        |          |0 = MII management command generation finished.
     * |        |          |1 = MII management command generation Enabled.
     * |[18]    |PREAMSP   |Preamble Suppress
     * |        |          |The PREAMSP controls the preamble field generation of MII management frame
     * |        |          |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped.
     * |        |          |0 = Preamble field generation of MII management frame not skipped.
     * |        |          |1 = Preamble field generation of MII management frame skipped.
     * |[19]    |MDCON     |MDC Clock ON
     * |        |          |The MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on.
     * |        |          |0 = MDC clock off.
     * |        |          |1 = MDC clock on.
     * @var EMAC_TypeDef::FFTCR
     * Offset: 0x9C  FIFO Threshold Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[1:0]   |RXTHD  |RXFIFO Low Threshold
     * |        |          |The RXTHD controls when RXDMA requests internal arbiter for data transfer between RXFIFO
     * |        |          |and system memory
     * |        |          |The RXTHD defines not only the high threshold of RXFIFO, but also the low threshold
     * |        |          |The low threshold is the half of high threshold always
     * |        |          |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to
     * |        |          |transfer frame data from RXFIFO to system memory
     * |        |          |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame
     * |        |          |data to system memory.
     * |        |          |00 = Depend on the burst length setting
     * |        |          |If the burst length is 8 words, high threshold is 8 words, too.
     * |        |          |01 = RXFIFO high threshold is 64B and low threshold is 32B.
     * |        |          |10 = RXFIFO high threshold is 128B and low threshold is 64B.
     * |        |          |11 = RXFIFO high threshold is 192B and low threshold is 96B.
     * |[9:8]   |TXTHD  |TXFIFO Low Threshold
     * |        |          |The TXTHD controls when TXDMA requests internal arbiter for data transfer between system
     * |        |          |memory and TXFIFO
     * |        |          |The TXTHD defines not only the low threshold of TXFIFO, but also the high threshold
     * |        |          |The high threshold is the twice of low threshold always
     * |        |          |During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops
     * |        |          |generate request to transfer frame data from system memory to TXFIFO
     * |        |          |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data
     * |        |          |from system memory to TXFIFO.
     * |        |          |The TXTHD also defines when the TXMAC starts to transmit frame out to network
     * |        |          |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold
     * |        |          |during the transmission of the frame
     * |        |          |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame
     * |        |          |out after the frame data are all inside the TXFIFO.
     * |        |          |00 = Undefined.
     * |        |          |01 = TXFIFO low threshold is 64B and high threshold is 128B.
     * |        |          |10 = TXFIFO low threshold is 80B and high threshold is 160B.
     * |        |          |11 = TXFIFO low threshold is 96B and high threshold is 192B.
     * |[21:20] |BURSTLEN  |DMA Burst Length
     * |        |          |This defines the burst length of AHB bus cycle while EMAC accesses system memory.
     * |        |          |00 = 4 words.
     * |        |          |01 = 8 words.
     * |        |          |10 = 16 words.
     * |        |          |11 = 16 words.
     * @var EMAC_TypeDef::TSDR
     * Offset: 0xA0  Transmit Start Demand Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |TXST      |Transmit Start Demand
     * |        |          |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled,
     * |        |          |the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted
     * |        |          |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write
     * |        |          |command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission.
     * |        |          |The EMAC_TXST is a write only register and read from this register is undefined.
     * |        |          |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state.
     * @var EMAC_TypeDef::RSDR
     * Offset: 0xA4  Receive Start Demand Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |RXST      |Receive Start Demand
     * |        |          |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled,
     * |        |          |the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted
     * |        |          |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write
     * |        |          |command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception.
     * |        |          |The EMAC_RXST is a write only register and read from this register is undefined.
     * |        |          |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state.
     * @var EMAC_TypeDef::DMARFC
     * Offset: 0xA8  Maximum Receive Frame Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[15:0]  |DMARFC      |Maximum Receive Frame Length
     * |        |          |The DMARFC defines the maximum frame length for received frame
     * |        |          |If the frame length of received frame is greater than DMARFC, and bit MFLEIEN (EMAC_MIEN[8])
     * |        |          |is also enabled, the bit MFLEIF (EMAC_MISTA[8]) is set and the RX interrupt is triggered.
     * |        |          |It is recommended that only use DMARFC to qualify the length of received frame while S/W wants to
     * |        |          |receive a frame which length is greater than 1518 bytes.
     * @var EMAC_TypeDef::MIEN
     * Offset: 0xAC  MAC Interrupt Enable Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |RXIEN     |Receive Interrupt Enable Bit
     * |        |          |The RXIEN controls the RX interrupt generation.
     * |        |          |If RXIEN is enabled and RXIF (EMAC_MISTA[0]) is high, EMAC generates the RX interrupt to CPU
     * |        |          |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_MISTA[15:1]
     * |        |          |is set and the corresponding bit of EMAC_MIEN is enabled
     * |        |          |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled
     * |        |          |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit.
     * |        |          |0 = RXIF (EMAC_MISTA[0]) is masked and RX interrupt generation Disabled.
     * |        |          |1 = RXIF (EMAC_MISTA[0]) is not masked and RX interrupt generation Enabled.
     * |[1]     |CRCEIEN   |CRC Error Interrupt Enable Bit
     * |        |          |The CRCEIEN controls the CRCEIF (EMAC_MISTA[1]) interrupt generation
     * |        |          |If CRCEIF (EMAC_MISTA[1]) is set, and both CRCEIEN and RXIEN (EMAC_MIEN[0]) are enabled, the
     * |        |          |EMAC generates the RX interrupt to CPU
     * |        |          |If CRCEIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |CRCEIF (EMAC_MISTA[1]) is set.
     * |        |          |0 = CRCEIF (EMAC_MISTA[1]) trigger RX interrupt Disabled.
     * |        |          |1 = CRCEIF (EMAC_MISTA[1]) trigger RX interrupt Enabled.
     * |[2]     |RXOVIEN   |Receive FIFO Overflow Interrupt Enable Bit
     * |        |          |The RXOVIEN controls the RXOVIF (EMAC_MISTA[2]) interrupt generation
     * |        |          |If RXOVIF (EMAC_MISTA[2]) is set, and both RXOVIEN and RXIEN (EMAC_MIEN[0]) are enabled, the
     * |        |          |EMAC generates the RX interrupt to CPU
     * |        |          |If RXOVIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |RXOVIF (EMAC_MISTA[2]) is set.
     * |        |          |0 = RXOVIF (EMAC_MISTA[2]) trigger RX interrupt Disabled.
     * |        |          |1 = RXOVIF (EMAC_MISTA[2]) trigger RX interrupt Enabled.
     * |[3]     |LPIEN     |Long Packet Interrupt Enable Bit
     * |        |          |The LPIEN controls the LPIF (EMAC_MISTA[3]) interrupt generation
     * |        |          |If LPIF (EMAC_MISTA[3]) is set, and both LPIEN and RXIEN (EMAC_MIEN[0]) are enabled, the EMAC
     * |        |          |generates the RX interrupt to CPU
     * |        |          |If LPIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF
     * |        |          |(EMAC_MISTA[3]) is set.
     * |        |          |0 = LPIF (EMAC_MISTA[3]) trigger RX interrupt Disabled.
     * |        |          |1 = LPIF (EMAC_MISTA[3]) trigger RX interrupt Enabled.
     * |[4]     |RXGDIEN   |Receive Good Interrupt Enable Bit
     * |        |          |The RXGDIEN controls the RXGDIF (EMAC_MISTA[4]) interrupt generation
     * |        |          |If RXGDIF (EMAC_MISTA[4]) is set, and both RXGDIEN and RXIEN (EMAC_MIEN[0]) are enabled, the
     * |        |          |EMAC generates the RX interrupt to CPU
     * |        |          |If RXGDIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |RXGDIF (EMAC_MISTA[4]) is set.
     * |        |          |0 = RXGDIF (EMAC_MISTA[4]) trigger RX interrupt Disabled.
     * |        |          |1 = RXGDIF (EMAC_MISTA[4]) trigger RX interrupt Enabled.
     * |[5]     |ALIEIEN   |Alignment Error Interrupt Enable Bit
     * |        |          |The ALIEIEN controls the ALIEIF (EMAC_MISTA[5]) interrupt generation
     * |        |          |If ALIEIF (EMAC_MISTA[5]) is set, and both ALIEIEN and RXIEN (EMAC_MIEN[0]) are enabled, the
     * |        |          |EMAC generates the RX interrupt to CPU
     * |        |          |If ALIEIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |ALIEIF (EMAC_MISTA[5]) is set.
     * |        |          |0 = ALIEIF (EMAC_MISTA[5]) trigger RX interrupt Disabled.
     * |        |          |1 = ALIEIF (EMAC_MISTA[5]) trigger RX interrupt Enabled.
     * |[6]     |RPIEN     |Runt Packet Interrupt Enable Bit
     * |        |          |The RPIEN controls the RPIF (EMAC_MISTA[6]) interrupt generation
     * |        |          |If RPIF (EMAC_MISTA[6]) is set, and both RPIEN and RXIEN (EMAC_MIEN[0]) are enabled, the EMAC
     * |        |          |generates the RX interrupt to CPU
     * |        |          |If RPIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |RPIF (EMAC_MISTA[6]) is set.
     * |        |          |0 = RPIF (EMAC_MISTA[6]) trigger RX interrupt Disabled.
     * |        |          |1 = RPIF (EMAC_MISTA[6]) trigger RX interrupt Enabled.
     * |[7]     |MPCOVIEN  |Miss Packet Counter Overrun Interrupt Enable Bit
     * |        |          |The MPCOVIEN controls the MPCOVIF (EMAC_MISTA[7]) interrupt generation
     * |        |          |If MPCOVIF (EMAC_MISTA[7]) is set, and both MPCOVIEN and RXIEN (EMAC_MIEN[0]) are enabled,
     * |        |          |the EMAC generates the RX interrupt to CPU
     * |        |          |If MPCOVIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |MPCOVIF (EMAC_MISTA[7]) is set.
     * |        |          |0 = MPCOVIF (EMAC_MISTA[7]) trigger RX interrupt Disabled.
     * |        |          |1 = MPCOVIF (EMAC_MISTA[7]) trigger RX interrupt Enabled.
     * |[8]     |MFLEIEN   |Maximum Frame Length Exceed Interrupt Enable Bit
     * |        |          |The MFLEIEN controls the MFLEIF (EMAC_MISTA[8]) interrupt generation
     * |        |          |If MFLEIF (EMAC_MISTA[8]) is set, and both MFLEIEN and RXIEN (EMAC_MIEN[0]) are enabled, the
     * |        |          |EMAC generates the RX interrupt to CPU
     * |        |          |If MFLEIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |MFLEIF (EMAC_MISTA[8]) is set.
     * |        |          |0 = MFLEIF (EMAC_MISTA[8]) trigger RX interrupt Disabled.
     * |        |          |1 = MFLEIF (EMAC_MISTA[8]) trigger RX interrupt Enabled.
     * |[9]     |DENIEN    |DMA Early Notification Interrupt Enable Bit
     * |        |          |The DENIEN controls the DENIF (EMAC_MISTA[9]) interrupt generation
     * |        |          |If DENIF (EMAC_MISTA[9]) is set, and both DENIEN and RXIEN (EMAC_MIEN[0]) are enabled, the
     * |        |          |EMAC generates the RX interrupt to CPU
     * |        |          |If DENIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |DENIF (EMAC_MISTA[9]) is set.
     * |        |          |0 = TDENIF (EMAC_MISTA[9]) trigger RX interrupt Disabled.
     * |        |          |1 = TDENIF (EMAC_MISTA[9]) trigger RX interrupt Enabled.
     * |[10]    |RDUIEN    |Receive Descriptor Unavailable Interrupt Enable Bit
     * |        |          |The RDUIEN controls the RDUIF (EMAC_MISTA[10]) interrupt generation
     * |        |          |If RDUIF (EMAC_MISTA[10]) is set, and both RDUIEN and RXIEN (EMAC_MIEN[0]) are enabled, the
     * |        |          |EMAC generates the RX interrupt to CPU
     * |        |          |If RDUIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |RDUIF (EMAC_MIOSTA[10]) register is set.
     * |        |          |0 = RDUIF (EMAC_MISTA[10]) trigger RX interrupt Disabled.
     * |        |          |1 = RDUIF (EMAC_MISTA[10]) trigger RX interrupt Enabled.
     * |[11]    |RXBEIEN   |Receive Bus Error Interrupt Enable Bit
     * |        |          |The RXBEIEN controls the RXBEIF (EMAC_MISTA[11]) interrupt generation
     * |        |          |If RXBEIF (EMAC_MISTA[11]) is set, and both RXBEIEN and RXIEN (EMAC_MIEN[0]) are enabled, the
     * |        |          |EMAC generates the RX interrupt to CPU
     * |        |          |If RXBEIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |RXBEIF (EMAC_MISTA[11]) is set.
     * |        |          |0 = RXBEIF (EMAC_MISTA[11]) trigger RX interrupt Disabled.
     * |        |          |1 = RXBEIF (EMAC_MISTA[11]) trigger RX interrupt Enabled.
     * |[14]    |CFRIEN    |Control Frame Receive Interrupt Enable Bit
     * |        |          |The CFRIEN controls the CFRIF (EMAC_MISTA[14]) interrupt generation
     * |        |          |If CFRIF (EMAC_MISTA[14]) is set, and both CFRIEN and RXIEN (EMAC_MIEN[0]) are enabled, the
     * |        |          |EMAC generates the RX interrupt to CPU
     * |        |          |If CFRIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |CFRIF (EMAC_MISTA[14]) register is set.
     * |        |          |0 = CFRIF (EMAC_MISTA[14]) trigger RX interrupt Disabled.
     * |        |          |1 = CFRIF (EMAC_MISTA[14]) trigger RX interrupt Enabled.
     * |[15]    |WOLIEN    |Wake on LAN Interrupt Enable Bit
     * |        |          |The WOLIEN controls the WOLIF (EMAC_MISTA[15]) interrupt generation
     * |        |          |If WOLIF (EMAC_MISTA[15]) is set, and both WOLIEN and RXIEN (EMAC_MIEN[0]) are enabled,
     * |        |          |the EMAC generates the RX interrupt to CPU
     * |        |          |If WOLIEN or RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the
     * |        |          |WOLIF (EMAC_MISTA[15]) is set.
     * |        |          |0 = WOLIF (EMAC_MISTA[15]) trigger RX interrupt Disabled.
     * |        |          |1 = WOLIF (EMAC_MISTA[15]) trigger RX interrupt Enabled.
     * |[16]    |TXIEN     |Transmit Interrupt Enable Bit
     * |        |          |The TXIEN controls the TX interrupt generation.
     * |        |          |If TXIEN is enabled and TXIF (EMAC_MISTA[16]) is high, EMAC generates the TX interrupt to CPU
     * |        |          |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of
     * |        |          |EMAC_MISTA[24:17] set and the corresponding bit of EMAC_MIEN is enabled
     * |        |          |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled
     * |        |          |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit.
     * |        |          |0 = TXIF (EMAC_MISTA[16]) is masked and TX interrupt generation Disabled.
     * |        |          |1 = TXIF (EMAC_MISTA[16]) is not masked and TX interrupt generation Enabled.
     * |[17]    |TXUDIEN   |Transmit FIFO Underflow Interrupt Enable Bit
     * |        |          |The TXUDIEN controls the TXUDIF (EMAC_MISTA[17]) interrupt generation
     * |        |          |If TXUDIF (EMAC_MISTA[17]) is set, and both TXUDIEN and TXIEN (EMAC_MIEN[16]) are enabled,
     * |        |          |the EMAC generates the TX interrupt to CPU
     * |        |          |If TXUDIEN or TXIEN (EMAC_MIEN[16]) is disabled, no TX interrupt is generated to CPU even
     * |        |          |the TXUDIF (EMAC_MISTA[17]) is set.
     * |        |          |0 = TXUDIF (EMAC_MISTA[17]) TX interrupt Disabled.
     * |        |          |1 = TXUDIF (EMAC_MISTA[17]) TX interrupt Enabled.
     * |[18]    |TXCPIEN   |Transmit Completion Interrupt Enable Bit
     * |        |          |The TXCPIEN controls the TXCPIF (EMAC_MISTA[18]) interrupt generation
     * |        |          |If TXCPIF (EMAC_MISTA[18]) is set, and both TXCPIEN and TXIEN (EMAC_MIEN[16]) are enabled,
     * |        |          |the EMAC generates the TX interrupt to CPU
     * |        |          |If TXCPIEN or TXIEN (EMAC_MIEN[16]) is disabled, no TX interrupt is generated to CPU even the
     * |        |          |TXCPIF (EMAC_MISTA[18]) is set.
     * |        |          |0 = TXCPIF (EMAC_MISTA[18]) trigger TX interrupt Disabled.
     * |        |          |1 = TXCPIF (EMAC_MISTA[18]) trigger TX interrupt Enabled.
     * |[19]    |EXDEFIEN  |Defer Exceed Interrupt Enable Bit
     * |        |          |The EXDEFIEN controls the EXDEFIF (EMAC_MISTA[19]) interrupt generation
     * |        |          |If EXDEFIF (EMAC_MISTA[19]) is set, and both EXDEFIEN and TXIEN (EMAC_MIEN[16]) are enabled,
     * |        |          |the EMAC generates the TX interrupt to CPU
     * |        |          |If EXDEFIEN or TXIEN (EMAC_MIEN[16]) is disabled, no TX interrupt is generated to CPU even the
     * |        |          |EXDEFIF (EMAC_MISTA[19]) is set.
     * |        |          |0 = EXDEFIF (EMAC_MISTA[19]) trigger TX interrupt Disabled.
     * |        |          |1 = EXDEFIF (EMAC_MISTA[19]) trigger TX interrupt Enabled.
     * |[20]    |NCSIEN    |No Carrier Sense Interrupt Enable Bit
     * |        |          |The NCSIEN controls the NCSIF (EMAC_MISTA[20]) interrupt generation
     * |        |          |If NCSIF (EMAC_MISTA[20]) is set, and both NCSIEN and TXIEN (EMAC_MIEN[16]) are enabled, the
     * |        |          |EMAC generates the TX interrupt to CPU
     * |        |          |If NCSIEN or TXIEN (EMAC_MIEN[16]) is disabled, no TX interrupt is generated to CPU even the
     * |        |          |NCSIF (EMAC_MISTA[20]) is set.
     * |        |          |0 = NCSIF (EMAC_MISTA[20]) trigger TX interrupt Disabled.
     * |        |          |1 = NCSIF (EMAC_MISTA[20]) trigger TX interrupt Enabled.
     * |[21]    |TXABTIEN  |Transmit Abort Interrupt Enable Bit
     * |        |          |The TXABTIEN controls the TXABTIF (EMAC_MISTA[21]) interrupt generation
     * |        |          |If TXABTIF (EMAC_MISTA[21]) is set, and both TXABTIEN and TXIEN (EMAC_MIEN[16]) are enabled,
     * |        |          |the EMAC generates the TX interrupt to CPU
     * |        |          |If TXABTIEN or TXIEN (EMAC_MIEN[16]) is disabled, no TX interrupt is generated to CPU even the
     * |        |          |TXABTIF (EMAC_MISTA[21]) is set.
     * |        |          |0 = TXABTIF (EMAC_MISTA[21]) trigger TX interrupt Disabled.
     * |        |          |1 = TXABTIF (EMAC_MISTA[21]) trigger TX interrupt Enabled.
     * |[22]    |LCIEN     |Late Collision Interrupt Enable Bit
     * |        |          |The LCIEN controls the LCIF (EMAC_MISTA[22]) interrupt generation
     * |        |          |If LCIF (EMAC_MISTA[22]) is set, and both LCIEN and TXIEN (EMAC_MIEN[16]) are enabled, the
     * |        |          |EMAC generates the TX interrupt to CPU
     * |        |          |If LCIEN or TXIEN (EMAC_MIEN[16]) is disabled, no TX interrupt is generated to CPU even the
     * |        |          |LCIF (EMAC_MISTA[22]) is set.
     * |        |          |0 = LCIF (EMAC_MISTA[22]) trigger TX interrupt Disabled.
     * |        |          |1 = LCIF (EMAC_MISTA[22]) trigger TX interrupt Enabled.
     * |[23]    |TDUIEN    |Transmit Descriptor Unavailable Interrupt Enable Bit
     * |        |          |The TDUIEN controls the TDUIF (EMAC_MISTA[23]) interrupt generation
     * |        |          |If TDUIF (EMAC_MISTA[23]) is set, and both TDUIEN and TXIEN (EMAC_MIEN[16]) are enabled, the
     * |        |          |EMAC generates the TX interrupt to CPU
     * |        |          |If TDUIEN or TXIEN (EMAC_MIEN[16]) is disabled, no TX interrupt is generated to CPU even the
     * |        |          |TDUIF (EMAC_MISTA[23]) is set.
     * |        |          |0 = TDUIF (EMAC_MISTA[23]) trigger TX interrupt Disabled.
     * |        |          |1 = TDUIF (EMAC_MISTA[23]) trigger TX interrupt Enabled.
     * |[24]    |TXBEIEN   |Transmit Bus Error Interrupt Enable Bit
     * |        |          |The TXBEIEN controls the TXBEIF (EMAC_MISTA[24]) interrupt generation
     * |        |          |If TXBEIF (EMAC_MISTA[24]) is set, and both TXBEIEN and TXIEN (EMAC_MIEN[16]) are enabled, the
     * |        |          |EMAC generates the TX interrupt to CPU
     * |        |          |If TXBEIEN or TXIEN (EMAC_MIEN[16]) is disabled, no TX interrupt is generated to CPU even the
     * |        |          |TXBEIF (EMAC_MISTA[24]) is set.
     * |        |          |0 = TXBEIF (EMAC_MISTA[24]) trigger TX interrupt Disabled.
     * |        |          |1 = TXBEIF (EMAC_MISTA[24]) trigger TX interrupt Enabled.
     * |[28]    |TSALMIEN  |Time Stamp Alarm Interrupt Enable Bit
     * |        |          |The TSALMIEN controls the TSALMIF (EMAC_MISTA[28]) interrupt generation
     * |        |          |If TSALMIF (EMAC_MISTA[28]) is set, and both TSALMIEN and TXIEN (EMAC_MIEN[16]) enabled, the
     * |        |          |EMAC generates the TX interrupt to CPU
     * |        |          |If TSALMIEN or TXIEN (EMAC_MIEN[16]) disabled, no TX interrupt generated to CPU even the
     * |        |          |TXTSALMIF (EMAC_MIEN[28]) is set.
     * |        |          |0 = TXTSALMIF (EMAC_MISTA[28]) trigger TX interrupt Disabled.
     * |        |          |1 = TXTSALMIF (EMAC_MISTA[28]) trigger TX interrupt Enabled.
     * @var EMAC_TypeDef::MISTA
     * Offset: 0xB0  MAC Interrupt Status Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |RXIF      |Receive Interrupt
     * |        |          |The RXIF indicates the RX interrupt status.
     * |        |          |If RXIF high and its corresponding enable bit, RXIEN (EMAC_MIEN[0]), is also high indicates
     * |        |          |the EMAC generates RX interrupt to CPU
     * |        |          |If RXIF is high but RXIEN (EMAC_MIEN[0]) is disabled, no RX interrupt is generated.
     * |        |          |The RXIF is logic OR result of bit logic AND result of EMAC_MISTA[15:1] and EMAC_MIEN[15:1]
     * |        |          |In other words, if any bit of EMAC_MISTA[15:1] is high and its corresponding enable bit in
     * |        |          |EMAC_MIEN[15:1] is also enabled, the RXIF will be high.
     * |        |          |Because the RXIF is a logic OR result, clears EMAC_MISTA[15:1] makes RXIF be cleared, too.
     * |        |          |0 = No status bit in EMAC_MISTA[15:1] is set or no enable bit in EMAC_MIEN[15:1] is enabled.
     * |        |          |1 = At least one status in EMAC_MISTA[15:1] is set and its corresponding enable bit in
     * |        |          |EMAC_MIEN[15:1] is enabled, too.
     * |[1]     |CRCEIF    |CRC Error Interrupt
     * |        |          |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped
     * |        |          |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and
     * |        |          |CRCEIF will not be set.
     * |        |          |If the CRCEIF is high and CRCEIEN (EMAC_MIEN[1]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the CRCEIF status.
     * |        |          |0 = The frame does not incur CRC error.
     * |        |          |1 = The frame incurred CRC error.
     * |[2]     |RXOVIF    |Receive FIFO Overflow Interrupt
     * |        |          |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception
     * |        |          |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer
     * |        |          |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control,
     * |        |          |the RXTHD of FFTCR register, to higher level.
     * |        |          |If the RXOVIF is high and RXOVIEN (EMAC_MIEN[2]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the RXOVIF status.
     * |        |          |0 = No RXFIFO overflow occurred during packet reception.
     * |        |          |1 = RXFIFO overflow occurred during packet reception.
     * |[3]     |LPIF      |Long Packet Interrupt Flag
     * |        |          |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the
     * |        |          |incoming packet is dropped
     * |        |          |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.
     * |        |          |If the LPIF is high and LPIEN (EMAC_MIEN[3]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the LPIF status.
     * |        |          |0 = The incoming frame is not a long frame or S/W wants to receive a long frame.
     * |        |          |1 = The incoming frame is a long frame and dropped.
     * |[4]     |RXGDIF    |Receive Good Interrupt
     * |        |          |The RXGDIF high indicates the frame reception has completed.
     * |        |          |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the RXGDIF status.
     * |        |          |0 = The frame reception has not complete yet.
     * |        |          |1 = The frame reception has completed.
     * |[5]     |ALIEIF    |Alignment Error Interrupt
     * |        |          |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte
     * |        |          |If the ALIEIF is high and ALIEIEN (EMAC_MIEN[5]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the ALIEIF status.
     * |        |          |0 = The frame length is a multiple of byte.
     * |        |          |1 = The frame length is not a multiple of byte.
     * |[6]     |RPIF      |Runt Packet Interrupt
     * |        |          |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped
     * |        |          |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set.
     * |        |          |If the RPIF is high and RPIEN (EMAC_MIEN[6]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the RPIF status.
     * |        |          |0 = The incoming frame is not a short frame or S/W wants to receive a short frame.
     * |        |          |1 = The incoming frame is a short frame and dropped.
     * |[7]     |MPCOVIF   |Missed Packet Counter Overrun Interrupt Flag
     * |        |          |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow
     * |        |          |If the MPCOVIF is high and MPCOVIEN (EMAC_MIEN[7]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the MPCOVIF status.
     * |        |          |0 = The MPCNT has not rolled over yet.
     * |        |          |1 = The MPCNT has rolled over yet.
     * |[8]     |MFLEIF    |Maximum Frame Length Exceed Interrupt Flag
     * |        |          |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation
     * |        |          |configured in DMARFC register and the incoming packet is dropped
     * |        |          |If the MFLEIF is high and MFLEIEN (EMAC_MIEN[8]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the MFLEIF status.
     * |        |          |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC.
     * |        |          |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC.
     * |[9]     |DENIF     |DMA Early Notification Interrupt
     * |        |          |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.
     * |        |          |If the DENIF is high and DENIENI (EMAC_MIEN[9]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the DENIF status.
     * |        |          |0 = The LENGTH field of incoming packet has not received yet.
     * |        |          |1 = The LENGTH field of incoming packet has received.
     * |[10]    |RDUIF     |Receive Descriptor Unavailable Interrupt
     * |        |          |The RDUIF high indicates that there is no available RX descriptor for packet reception and
     * |        |          |RXDMA will stay at Halt state
     * |        |          |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to
     * |        |          |make RXDMA leave Halt state while new RX descriptor is available.
     * |        |          |If the RDUIF is high and RDUIEN (EMAC_MIEN[10]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the RDUIF status.
     * |        |          |0 = RX descriptor is available.
     * |        |          |1 = RX descriptor is unavailable.
     * |[11]    |RXBEIF    |Receive Bus Error Interrupt
     * |        |          |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access
     * |        |          |system memory through RXDMA during packet reception process
     * |        |          |Reset EMAC is recommended while RXBEIF status is high.
     * |        |          |If the RXBEIF is high and RXBEIEN (EMAC_MIEN[11]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the RXBEIF status.
     * |        |          |0 = No ERROR response is received.
     * |        |          |1 = ERROR response is received.
     * |[14]    |CFRIF     |Control Frame Receive Interrupt
     * |        |          |The CFRIF high indicates EMAC receives a flow control frame
     * |        |          |The CFRIF only available while EMAC is operating on full duplex mode.
     * |        |          |If the CFRIF is high and CFRIEN (EMAC_MIEN[14]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the CFRIF status.
     * |        |          |0 = The EMAC does not receive the flow control frame.
     * |        |          |1 = The EMAC receives a flow control frame.
     * |[15]    |WOLIF     |Wake on LAN Interrupt Flag
     * |        |          |The WOLIF high indicates EMAC receives a Magic Packet
     * |        |          |The CFRIF only available while system is in power down mode and WOLEN is set high.
     * |        |          |If the WOLIF is high and WOLIEN (EMAC_MIEN[15]) is enabled, the RXIF will be high
     * |        |          |Write 1 to this bit clears the WOLIF status.
     * |        |          |0 = The EMAC does not receive the Magic Packet.
     * |        |          |1 = The EMAC receives a Magic Packet.
     * |[16]    |TXIF      |Transmit Interrupt
     * |        |          |The TXIF indicates the TX interrupt status.
     * |        |          |If TXIF high and its corresponding enable bit, TXIEN (EMAC_MIEN[16]), is also high indicates
     * |        |          |the EMAC generates TX interrupt to CPU
     * |        |          |If TXIF is high but TXIEN (EMAC_MIEN[16]) is disabled, no TX interrupt is generated.
     * |        |          |The TXIF is logic OR result of bit logic AND result of EMAC_MISTA[28:17] and EMAC_MIEN[28:17]
     * |        |          |In other words, if any bit of EMAC_MISTA[28:17] is high and its corresponding enable bit
     * |        |          |in EMAC_MIEN[28:17] is also enabled, the TXIF will be high
     * |        |          |Because the TXIF is a logic OR result, clears EMAC_MISTA[28:17] makes TXIF be cleared, too.
     * |        |          |0 = No status bit in EMAC_MISTA[28:17] is set or no enable bit in EMAC_MIEN[28:17] is enabled.
     * |        |          |1 = At least one status in EMAC_MISTA[28:17] is set and its corresponding enable bit
     * |        |          |in EMAC_MIEN[28:17] is enabled, too.
     * |[17]    |TXUDIF    |Transmit FIFO Underflow Interrupt
     * |        |          |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission
     * |        |          |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically
     * |        |          |without S/W intervention
     * |        |          |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control,
     * |        |          |the TXTHD of FFTCR register, to higher level.
     * |        |          |If the TXUDIF is high and TXUDIEN (EMAC_MIEN[17]) is enabled, the TXIF will be high
     * |        |          |Write 1 to this bit clears the TXUDIF status.
     * |        |          |0 = No TXFIFO underflow occurred during packet transmission.
     * |        |          |1 = TXFIFO underflow occurred during packet transmission.
     * |[18]    |TXCPIF    |Transmit Completion Interrupt
     * |        |          |The TXCPIF indicates the packet transmission has completed correctly.
     * |        |          |If the TXCPIF is high and TXCPIEN (EMAC_MIEN[18]) is enabled, the TXIF will be high
     * |        |          |Write 1 to this bit clears the TXCPIF status.
     * |        |          |0 = The packet transmission not completed.
     * |        |          |1 = The packet transmission has completed.
     * |[19]    |EXDEFIF   |Defer Exceed Interrupt
     * |        |          |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms
     * |        |          |on 100Mbps mode, or 3.2768ms on 10Mbps mode.
     * |        |          |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC
     * |        |          |is operating on half-duplex mode.
     * |        |          |If the EXDEFIF is high and EXDEFIEN (EMAC_MIEN[19]) is enabled, the TXIF will be high
     * |        |          |Write 1 to this bit clears the EXDEFIF status.
     * |        |          |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
     * |        |          |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
     * |[20]    |NCSIF     |No Carrier Sense Interrupt
     * |        |          |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during
     * |        |          |the packet transmission
     * |        |          |The NCSIF is only available while EMAC is operating on half-duplex mode
     * |        |          |If the NCSIF is high and NCSIEN (EMAC_MIEN[20]) is enabled, the TXIF will be high.
     * |        |          |Write 1 to this bit clears the NCSIF status.
     * |        |          |0 = CRS signal actives correctly.
     * |        |          |1 = CRS signal does not active at the start of or during the packet transmission.
     * |[21]    |TXABTIF   |Transmit Abort Interrupt
     * |        |          |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission,
     * |        |          |and then the transmission process for this packet is aborted
     * |        |          |The transmission abort is only available while EMAC is operating on half-duplex mode.
     * |        |          |If the TXABTIF is high and TXABTIEN (EMAC_MIEN[21]) is enabled, the TXIF will be high
     * |        |          |Write 1 to this bit clears the TXABTIF status.
     * |        |          |0 = Packet does not incur 16 consecutive collisions during transmission.
     * |        |          |1 = Packet incurred 16 consecutive collisions during transmission.
     * |[22]    |LCIF      |Late Collision Interrupt
     * |        |          |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window
     * |        |          |This means after the 64 bytes of a frame has been transmitted out to the network, the collision
     * |        |          |still occurred.
     * |        |          |The late collision check will only be done while EMAC is operating on half-duplex mode
     * |        |          |If the LCIF is high and LCIEN (EMAC_MIEN[22]) is enabled, the TXIF will be high.
     * |        |          |Write 1 to this bit clears the LCIF status.
     * |        |          |0 = No collision occurred in the outside of 64 bytes collision window.
     * |        |          |1 = Collision occurred in the outside of 64 bytes collision window.
     * |[23]    |TDUIF     |Transmit Descriptor Unavailable Interrupt
     * |        |          |The TDUIF high indicates that there is no available TX descriptor for packet transmission and
     * |        |          |TXDMA will stay at Halt state.
     * |        |          |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make
     * |        |          |TXDMA leave Halt state while new TX descriptor is available.
     * |        |          |If the TDUIF is high and TDUIEN (EMAC_MIEN[23]) is enabled, the TXIF will be high.
     * |        |          |Write 1 to this bit clears the TDUIF status.
     * |        |          |0 = TX descriptor is available.
     * |        |          |1 = TX descriptor is unavailable.
     * |[24]    |TXBEIF    |Transmit Bus Error Interrupt
     * |        |          |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system
     * |        |          |memory through TXDMA during packet transmission process
     * |        |          |Reset EMAC is recommended while TXBEIF status is high.
     * |        |          |If the TXBEIF is high and TXBEIEN (EMAC_MIEN[24]) is enabled, the TXIF will be high.
     * |        |          |Write 1 to this bit clears the TXBEIF status.
     * |        |          |0 = No ERROR response is received.
     * |        |          |1 = ERROR response is received.
     * |[28]    |TSALMIF   |Time Stamp Alarm Interrupt
     * |        |          |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and
     * |        |          |EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBLSR.
     * |        |          |If TSALMIF is high and TSALMIEN (EMAC_MIEN[28]) enabled, the TXIF will be high.
     * |        |          |Write 1 to this bit clears the TSALMIF status.
     * |        |          |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC.
     * |        |          |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC.
     * @var EMAC_TypeDef::MGSTA
     * Offset: 0xB4  MAC General Status Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |CFR       |Control Frame Received
     * |        |          |The CFRIF high indicates EMAC receives a flow control frame
     * |        |          |The CFRIF only available while EMAC is operating on full duplex mode.
     * |        |          |0 = The EMAC does not receive the flow control frame.
     * |        |          |1 = The EMAC receives a flow control frame.
     * |[1]     |RXHALT    |Receive Halted
     * |        |          |The RXHALT high indicates the next normal packet reception process will be halted because
     * |        |          |the bit RXON of MCMDR is disabled be S/W.
     * |        |          |0 = Next normal packet reception process will go on.
     * |        |          |1 = Next normal packet reception process will be halted.
     * |[2]     |RXFFULL   |RXFIFO Full
     * |        |          |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO
     * |        |          |and the following incoming packet will be dropped.
     * |        |          |0 = The RXFIFO is not full.
     * |        |          |1 = The RXFIFO is full and the following incoming packet will be dropped.
     * |[7:4]   |COLCNT    |Collision Count
     * |        |          |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission
     * |        |          |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be
     * |        |          |0 and bit TXABTIF will be set to 1.
     * |[8]     |DEF       |Deferred Transmission
     * |        |          |The DEF high indicates the packet transmission has deferred once
     * |        |          |The DEF is only available while EMAC is operating on half-duplex mode.
     * |        |          |0 = Packet transmission does not defer.
     * |        |          |1 = Packet transmission has deferred once.
     * |[9]     |TXPAUSED  |Transmission Paused
     * |        |          |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally
     * |        |          |because EMAC received a PAUSE control frame.
     * |        |          |0 = Next normal packet transmission process will go on.
     * |        |          |1 = Next normal packet transmission process will be paused.
     * |[10]    |SQE       |Signal Quality Error
     * |        |          |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode
     * |        |          |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC
     * |        |          |is operating on 10Mbps half-duplex mode.
     * |        |          |0 = No SQE error found at end of packet transmission.
     * |        |          |1 = SQE error found at end of packet transmission.
     * |[11]    |TXHALT    |Transmission Halted
     * |        |          |The TXHALT high indicates the next normal packet transmission process will be halted because
     * |        |          |the bit TXON (EMAC_CTL[8]) is disabled be S/W.
     * |        |          |0 = Next normal packet transmission process will go on.
     * |        |          |1 = Next normal packet transmission process will be halted.
     * |[12]    |RPSTS     |Remote Pause Status
     * |        |          |The RPSTS indicates that remote pause counter down counting actives.
     * |        |          |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause
     * |        |          |counter down counting
     * |        |          |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet
     * |        |          |transmission until the down counting done.
     * |        |          |0 = Remote pause counter down counting done.
     * |        |          |1 = Remote pause counter down counting actives.
     * @var EMAC_TypeDef::MPCNT
     * Offset: 0xB8  Missed Packet Count Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[15:0]  |MPCNT     |Miss Packet Count
     * |        |          |The MPCNT indicates the number of packets that were dropped due to various types of receive errors
     * |        |          |The following type of receiving error makes missed packet counter increase:
     * |        |          |1. Incoming packet is incurred RXFIFO overflow.
     * |        |          |2. Incoming packet is dropped due to RXON is disabled.
     * |        |          |3. Incoming packet is incurred CRC error.
     * @var EMAC_TypeDef::MRPC
     * Offset: 0xBC  MAC Receive Pause Count Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[15:0]  |MRPC     |MAC Receive Pause Count
     * |        |          |The MRPC keeps the OPERAND field of the PAUSE control frame
     * |        |          |It indicates how many slot time (512 bit time) the TX of EMAC will be paused.
     * @var EMAC_TypeDef::DMARFS
     * Offset: 0xC8  DMA Receive Frame Status Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[15:0]  |RXFLT     |Receive Frame LENGTH
     * |        |          |The RXFLT keeps the LENGTH field of each incoming Ethernet packet
     * |        |          |If the bit DENIEN (EMAC_MIEN[9]) is enabled and the LENGTH field of incoming packet has
     * |        |          |received, the bit DENIF (EMAC_MISTA[9]) will be set and trigger interrupt.
     * |        |          |And, the content of LENGTH field will be stored in RXFLT.
     * @var EMAC_TypeDef::CTXDSA
     * Offset: 0xCC  Current Transmit Descriptor Start Address Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |CTXDSA    |Current Transmit Descriptor Start Address
     * |        |          |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently
     * |        |          |The CTXDSA is read only and write to this register has no effect.
     * @var EMAC_TypeDef::CTXBSA
     * Offset: 0xD0  Current Transmit Buffer Start Address Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |CTXBSA    |Current Transmit Buffer Start Address
     * |        |          |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently
     * |        |          |The CTXBSA is read only and write to this register has no effect.
     * @var EMAC_TypeDef::CRXDSA
     * Offset: 0xD4  Current Receive Descriptor Start Address Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |CRXDSA    |Current Receive Descriptor Start Address
     * |        |          |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently
     * |        |          |The CRXDSA is read only and write to this register has no effect.
     * @var EMAC_TypeDef::CRXBSA
     * Offset: 0xD8  Current Receive Buffer Start Address Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |CRXBSA    |Current Receive Buffer Start Address
     * |        |          |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently
     * |        |          |The CRXBSA is read only and write to this register has no effect.
     * @var EMAC_TypeDef::TSCTL
     * Offset: 0x100  Time Stamp Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |TSEN      |Time Stamp Function Enable Bit
     * |        |          |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not.
     * |        |          |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low
     * |        |          |to disable IEEE 1588 PTP time stamp function.
     * |        |          |0 = I EEE 1588 PTP time stamp function Disabled.
     * |        |          |1 = IEEE 1588 PTP time stamp function Enabled.
     * |[1]     |TSIEN     |Time Stamp Counter Initialization Enable Bit
     * |        |          |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC
     * |        |          |and EMAC_UPDSUBSEC to PTP time stamp counter.
     * |        |          |After the load operation finished, Ethernet MAC controller clear this bit to low automatically.
     * |        |          |0 = Time stamp counter initialization done.
     * |        |          |1 = Time stamp counter initialization Enabled.
     * |[2]     |TSMODE    |Time Stamp Fine Update Enable Bit
     * |        |          |This bit chooses the time stamp counter update mode.
     * |        |          |0 = Time stamp counter is in coarse update mode.
     * |        |          |1 = Time stamp counter is in fine update mode.
     * |[3]     |TSUPDATE  |Time Stamp Counter Time Update Enable Bit
     * |        |          |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and
     * |        |          |EMAC_UPDSUBSEC to PTP time stamp counter.
     * |        |          |After the add operation finished, Ethernet MAC controller clear this bit to low automatically.
     * |        |          |0 = No action.
     * |        |          |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC.
     * |[5]     |TSALMEN   |Time Stamp Alarm Enable Bit
     * |        |          |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_MISTA[28]) high when
     * |        |          |EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
     * |        |          |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
     * |        |          |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
     * @var EMAC_TypeDef::TSSEC
     * Offset: 0x110  Time Stamp Counter Second Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |SEC       |Time Stamp Counter Second
     * |        |          |This register reflects the bit [63:32] value of 64-bit reference timing counter
     * |        |          |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
     * @var EMAC_TypeDef::TSSUBSEC
     * Offset: 0x114  Time Stamp Counter Sub Second Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |SUBSEC    |Time Stamp Counter Sub-second
     * |        |          |This register reflects the bit [31:0] value of 64-bit reference timing counter
     * |        |          |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
     * @var EMAC_TypeDef::TSINC
     * Offset: 0x118  Time Stamp Increment Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[7:0]   |CNTINC    |Time Stamp Counter Increment
     * |        |          |Time stamp counter increment value.
     * |        |          |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every
     * |        |          |time when it wants to increase the EMAC_TSSUBSEC value.
     * @var EMAC_TypeDef::TSADDEND
     * Offset: 0x11C  Time Stamp Addend Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |ADDEND    |Time Stamp Counter Addend
     * |        |          |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.
     * |        |          |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator
     * |        |          |with this 32-bit value in each HCLK
     * |        |          |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit
     * |        |          |value kept in register EMAC_TSINC.
     * @var EMAC_TypeDef::TSUPDSEC
     * Offset: 0x120  Time Stamp Update Second Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |SEC       |Time Stamp Counter Second Update
     * |        |          |When TSIEN (EMAC_TSCTL[1]) is high
     * |        |          |EMAC loads this 32-bit value to EMAC_TSSEC directly
     * |        |          |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value.
     * @var EMAC_TypeDef::TSUPDSUBSEC
     * Offset: 0x124  Time Stamp Update Sub Second Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |SUBSEC    |Time Stamp Counter Sub-second Update
     * |        |          |When TSIEN (EMAC_TSCTL[1]) is high
     * |        |          |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly
     * |        |          |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value.
     * @var EMAC_TypeDef::TSALMSEC
     * Offset: 0x128  Time Stamp Alarm Second Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |SEC       |Time Stamp Counter Second Alarm
     * |        |          |Time stamp counter second part alarm value.
     * |        |          |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
     * |        |          |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
     * |        |          |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_MISTA[28]) high.
     * @var EMAC_TypeDef::TSALMSUBSEC
     * Offset: 0x12C  Time Stamp Alarm Sub Second Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[31:0]  |SUBSEC    |Time Stamp Counter Sub-second Alarm
     * |        |          |Time stamp counter sub-second part alarm value.
     * |        |          |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
     * |        |          |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
     * |        |          |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_MISTA[28]) high.
     */
    __IO UINT32 CAMCMR;                /*!< [0x0000] CAM Comparison Register */
    __IO UINT32 CAMEN;                 /*!< [0x0004] CAM Enable Register */
    struct {
    __IO UINT32 CAMxMsb;               /*!< [0x0008+(x)*0x8] CAMx Most Significant Word Register */
    __IO UINT32 CAMxLsb;               /*!< [0x000c+(x)*0x8] CAMx Least Significant Word Register */
    } CAMx[15];
    __IO UINT32 CAM15Msb;              /*!< [0x0080] CAM15 Most Significant Word Register */
    __IO UINT32 CAM15Lsb;              /*!< [0x0084] CAM15 Least Significant Word Register */
    __IO UINT32 TXDLSA;                /*!< [0x0088] Transmit Descriptor Link List Start Address Register */
    __IO UINT32 RXDLSA;                /*!< [0x008c] Receive Descriptor Link List Start Address Register */
    __IO UINT32 MCMDR;                 /*!< [0x0090] MAC Command Register */
    __IO UINT32 MIID;                  /*!< [0x0094] MII Management Data Register */
    __IO UINT32 MIIDA;                 /*!< [0x0098] MII Management Control and Address Register */
    __IO UINT32 FFTCR;                 /*!< [0x009c] FIFO Threshold Control Register */
    __O  UINT32 TSDR;                  /*!< [0x00a0] Transmit Start Demand Register */
    __O  UINT32 RSDR;                  /*!< [0x00a4] Receive Start Demand Register */
    __IO UINT32 DMARFC;                /*!< [0x00a8] Maximum Receive Frame Control Register */
    __IO UINT32 MIEN;                  /*!< [0x00ac] MAC Interrupt Enable Register */
    __IO UINT32 MISTA;                 /*!< [0x00b0] MAC Interrupt Status Register */
    __IO UINT32 MGSTA;                 /*!< [0x00b4] MAC General Status Register */
    __IO UINT32 MPCNT;                 /*!< [0x00b8] Missed Packet Count Register */
    __I  UINT32 MRPC;                  /*!< [0x00bc] MAC Receive Pause Count Register */
    /** @cond HIDDEN_SYMBOLS */
    __I  UINT32 RESERVE0[2];
    /** @endcond */
    __IO UINT32 DMARFS;                /*!< [0x00c8] DMA Receive Frame Status Register */
    __I  UINT32 CTXDSA;                /*!< [0x00cc] Current Transmit Descriptor Start Address Register */
    __I  UINT32 CTXBSA;                /*!< [0x00d0] Current Transmit Buffer Start Address Register */
    __I  UINT32 CRXDSA;                /*!< [0x00d4] Current Receive Descriptor Start Address Register */
    __I  UINT32 CRXBSA;                /*!< [0x00d8] Current Receive Buffer Start Address Register */
    /** @cond HIDDEN_SYMBOLS */
    __I  UINT32 RESERVE1[9];
    /** @endcond */
    __IO UINT32 TSCTL;                 /*!< [0x0100] Time Stamp Control Register */
    /** @cond HIDDEN_SYMBOLS */
    __I  UINT32 RESERVE2[3];
    /** @endcond */
    __I  UINT32 TSSEC;                 /*!< [0x0110] Time Stamp Counter Second Register */
    __I  UINT32 TSSUBSEC;              /*!< [0x0114] Time Stamp Counter Sub Second Register */
    __IO UINT32 TSINC;                 /*!< [0x0118] Time Stamp Increment Register */
    __IO UINT32 TSADDEND;              /*!< [0x011c] Time Stamp Addend Register */
    __IO UINT32 TSUPDSEC;              /*!< [0x0120] Time Stamp Update Second Register */
    __IO UINT32 TSUPDSUBSEC;           /*!< [0x0124] Time Stamp Update Sub Second Register */
    __IO UINT32 TSALMSEC;              /*!< [0x0128] Time Stamp Alarm Second Register */
    __IO UINT32 TSALMSUBSEC;           /*!< [0x012c] Time Stamp Alarm Sub Second Register */
} EMAC_TypeDef;

/** Tx/Rx buffer descriptor structure */
typedef struct
{
    UINT32 u32Status1;   /*!<  Status word 1 */
    UINT32 u32Data;      /*!<  Pointer to data buffer */
    UINT32 u32Status2;   /*!<  Status word 2 */
    UINT32 u32Next;      /*!<  Pointer to next descriptor */
    UINT32 u32Backup1;   /*!<  For backup descriptor fields over written by time stamp */
    UINT32 u32Backup2;   /*!<  For backup descriptor fields over written by time stamp */
} EMAC_DESCRIPTOR_T;

/** Tx/Rx buffer structure */
typedef struct
{
    uint8_t au8Buf[EMAC_MAX_PKT_SIZE];
} EMAC_FRAME_T;

typedef struct
{
    EMAC_TypeDef  *psEmac;

    uint32_t u32TxDescSize;
    uint32_t u32RxDescSize;

    EMAC_DESCRIPTOR_T *psRXDescs;
    EMAC_FRAME_T *psRXFrames;
    EMAC_DESCRIPTOR_T *psTXDescs;
    EMAC_FRAME_T *psTXFrames;

    EMAC_DESCRIPTOR_T *psCurrentTxDesc;
    EMAC_DESCRIPTOR_T *psNextTxDesc;
    EMAC_DESCRIPTOR_T *psCurrentRxDesc;

} EMAC_MEMMGR_T;

#define EMAC0    ((EMAC_TypeDef *)EMC0_BA)
#define EMAC1    ((EMAC_TypeDef *)EMC1_BA)

/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
  @{
*/


/**
  * @brief  Enable EMAC Tx function
  * @param  None
  * @return None
  * \hideinitializer
  */
#define EMAC_ENABLE_TX(EMAC) (EMAC->MCMDR |= EMAC_MCMDR_TXON_Msk)


/**
  * @brief  Enable EMAC Rx function
  * @param  The pointer of the specified EMAC module
  * @return None
  * \hideinitializer
  */
#define EMAC_ENABLE_RX(EMAC) do{EMAC->MCMDR |= EMAC_MCMDR_RXON_Msk; EMAC->RSDR = 0;}while(0)

/**
  * @brief  Disable EMAC Tx function
  * @param  The pointer of the specified EMAC module
  * @return None
  * \hideinitializer
  */
#define EMAC_DISABLE_TX(EMAC) (EMAC->MCMDR &= ~EMAC_MCMDR_TXON_Msk)


/**
  * @brief  Disable EMAC Rx function
  * @param  The pointer of the specified EMAC module
  * @return None
  * \hideinitializer
  */
#define EMAC_DISABLE_RX(EMAC) (EMAC->MCMDR &= ~EMAC_MCMDR_RXON_Msk)

/**
  * @brief  Enable EMAC Magic Packet Wakeup function
  * @param  The pointer of the specified EMAC module
  * @return None
  * \hideinitializer
  */
#define EMAC_ENABLE_MAGIC_PKT_WAKEUP(EMAC) (EMAC->MCMDR |= EMAC_MCMDR_WOLEN_Msk)

/**
  * @brief  Disable EMAC Magic Packet Wakeup function
  * @param  The pointer of the specified EMAC module
  * @return None
  * \hideinitializer
  */
#define EMAC_DISABLE_MAGIC_PKT_WAKEUP(EMAC) (EMAC->MCMDR &= ~EMAC_MCMDR_WOLEN_Msk)

/**
  * @brief  Enable EMAC to receive broadcast packets
  * @param  The pointer of the specified EMAC module
  * @return None
  * \hideinitializer
  */
#define EMAC_ENABLE_RECV_BCASTPKT(EMAC) (EMAC->CAMCMR |= EMAC_CAMCMR_ABP_Msk)

/**
  * @brief  Disable EMAC to receive broadcast packets
  * @param  The pointer of the specified EMAC module
  * @return None
  * \hideinitializer
  */
#define EMAC_DISABLE_RECV_BCASTPKT(EMAC) (EMAC->CAMCMR &= ~EMAC_CAMCMR_ABP_Msk)

/**
  * @brief  Enable EMAC to receive multicast packets
  * @param  The pointer of the specified EMAC module
  * @return None
  * \hideinitializer
  */
#define EMAC_ENABLE_RECV_MCASTPKT(EMAC) (EMAC->CAMCMR |= EMAC_CAMCMR_AMP_Msk)

/**
  * @brief  Disable EMAC Magic Packet Wakeup function
  * @param  The pointer of the specified EMAC module
  * @return None
  * \hideinitializer
  */
#define EMAC_DISABLE_RECV_MCASTPKT(EMAC) (EMAC->CAMCMR &= ~EMAC_CAMCMR_AMP_Msk)

/**
  * @brief  Check if EMAC time stamp alarm interrupt occurred or not
  * @param  The pointer of the specified EMAC module
  * @return If time stamp alarm interrupt occurred or not
  * @retval 0 Alarm interrupt does not occur
  * @retval 1 Alarm interrupt occurred
  * \hideinitializer
  */
#define EMAC_GET_ALARM_FLAG(EMAC) (EMAC->MISTA & EMAC_MISTA_TSALMIF_Msk ? 1 : 0)

/**
  * @brief  Clear EMAC time stamp alarm interrupt flag
  * @param  The pointer of the specified EMAC module
  * @return None
  * \hideinitializer
  */
#define EMAC_CLR_ALARM_FLAG(EMAC) (EMAC->MISTA = EMAC_MISTA_TSALMIF_Msk)

/**
  * @brief  Trigger EMAC Rx function
  * @param  The pointer of the specified EMAC module
  * @return None
  */
#define EMAC_TRIGGER_RX(EMAC) do{EMAC->RSDR = 0UL;}while(0)

/**
  * @brief  Trigger EMAC Tx function
  * @param  The pointer of the specified EMAC module
  * @return None
  */
#define EMAC_TRIGGER_TX(EMAC) do{EMAC->TSDR = 0UL;}while(0)

/**
 *    @brief        Enable specified EMAC interrupt
 *
 *    @param[in]    EMAC        The pointer of the specified EMAC module
 *    @param[in]    u32eIntSel  Interrupt type select
 *                              - \ref EMAC_MIEN_RXIEN_Msk    : Receive
 *                              - \ref EMAC_MIEN_CRCEIEN_Msk  : CRC Error
 *                              - \ref EMAC_MIEN_RXOVIEN_Msk  : Receive FIFO Overflow
 *                              - \ref EMAC_MIEN_LPIEN_Msk    : Long Packet
 *                              - \ref EMAC_MIEN_RXGDIEN_Msk  : Receive Good
 *                              - \ref EMAC_MIEN_ALIEIEN_Msk  : Alignment Error
 *                              - \ref EMAC_MIEN_RPIEN_Msk    : Runt Packet
 *                              - \ref EMAC_MIEN_MPCOVIEN_Msk : Miss Packet Counter Overrun
 *                              - \ref EMAC_MIEN_MFLEIEN_Msk  : Maximum Frame Length Exceed
 *                              - \ref EMAC_MIEN_DENIEN_Msk   : DMA Early Notification
 *                              - \ref EMAC_MIEN_RDUIEN_Msk   : Receive Descriptor Unavailable
 *                              - \ref EMAC_MIEN_RXBEIEN_Msk  : Receive Bus Error
 *                              - \ref EMAC_MIEN_CFRIEN_Msk   : Control Frame Receive
 *                              - \ref EMAC_MIEN_WOLIEN_Msk   : Wake on LAN Interrupt
 *                              - \ref EMAC_MIEN_TXIEN_Msk    : Transmit
 *                              - \ref EMAC_MIEN_TXUDIEN_Msk  : Transmit FIFO Underflow
 *                              - \ref EMAC_MIEN_TXCPIEN_Msk  : Transmit Completion
 *                              - \ref EMAC_MIEN_EXDEFIEN_Msk : Defer Exceed
 *                              - \ref EMAC_MIEN_NCSIEN_Msk   : No Carrier Sense
 *                              - \ref EMAC_MIEN_TXABTIEN_Msk : Transmit Abort
 *                              - \ref EMAC_MIEN_LCIEN_Msk    : Late Collision
 *                              - \ref EMAC_MIEN_TDUIEN_Msk   : Transmit Descriptor Unavailable
 *                              - \ref EMAC_MIEN_TXBEIEN_Msk  : Transmit Bus Error
 *                              - \ref EMAC_MIEN_TSALMIEN_Msk : Time Stamp Alarm
 *
 *    @return       None
 *
 *    @details      This macro enable specified EMAC interrupt.
 *    \hideinitializer
 */
#define EMAC_ENABLE_INT(EMAC, u32eIntSel)    ((EMAC)->MIEN |= (u32eIntSel))

/**
 *    @brief        Disable specified EMAC interrupt
 *
 *    @param[in]    EMAC        The pointer of the specified EMAC module
 *    @param[in]    u32eIntSel  Interrupt type select
 *                              - \ref EMAC_MIEN_RXIEN_Msk    : Receive
 *                              - \ref EMAC_MIEN_CRCEIEN_Msk  : CRC Error
 *                              - \ref EMAC_MIEN_RXOVIEN_Msk  : Receive FIFO Overflow
 *                              - \ref EMAC_MIEN_LPIEN_Msk    : Long Packet
 *                              - \ref EMAC_MIEN_RXGDIEN_Msk  : Receive Good
 *                              - \ref EMAC_MIEN_ALIEIEN_Msk  : Alignment Error
 *                              - \ref EMAC_MIEN_RPIEN_Msk    : Runt Packet
 *                              - \ref EMAC_MIEN_MPCOVIEN_Msk : Miss Packet Counter Overrun
 *                              - \ref EMAC_MIEN_MFLEIEN_Msk  : Maximum Frame Length Exceed
 *                              - \ref EMAC_MIEN_DENIEN_Msk   : DMA Early Notification
 *                              - \ref EMAC_MIEN_RDUIEN_Msk   : Receive Descriptor Unavailable
 *                              - \ref EMAC_MIEN_RXBEIEN_Msk  : Receive Bus Error
 *                              - \ref EMAC_MIEN_CFRIEN_Msk   : Control Frame Receive
 *                              - \ref EMAC_MIEN_WOLIEN_Msk   : Wake on LAN Interrupt
 *                              - \ref EMAC_MIEN_TXIEN_Msk    : Transmit
 *                              - \ref EMAC_MIEN_TXUDIEN_Msk  : Transmit FIFO Underflow
 *                              - \ref EMAC_MIEN_TXCPIEN_Msk  : Transmit Completion
 *                              - \ref EMAC_MIEN_EXDEFIEN_Msk : Defer Exceed
 *                              - \ref EMAC_MIEN_NCSIEN_Msk   : No Carrier Sense
 *                              - \ref EMAC_MIEN_TXABTIEN_Msk : Transmit Abort
 *                              - \ref EMAC_MIEN_LCIEN_Msk    : Late Collision
 *                              - \ref EMAC_MIEN_TDUIEN_Msk   : Transmit Descriptor Unavailable
 *                              - \ref EMAC_MIEN_TXBEIEN_Msk  : Transmit Bus Error
 *                              - \ref EMAC_MIEN_TSALMIEN_Msk : Time Stamp Alarm
 *
 *    @return       None
 *
 *    @details      This macro disable specified EMAC interrupt.
 *    \hideinitializer
 */
#define EMAC_DISABLE_INT(EMAC, u32eIntSel)    ((EMAC)->MIEN &= ~ (u32eIntSel))

/**
 *    @brief        Get specified interrupt flag/status
 *
 *    @param[in]    EMAC            The pointer of the specified EMAC module
 *    @param[in]    u32eIntTypeFlag Interrupt Type Flag, should be
 *                                  - \ref EMAC_MISTA_RXIF_Msk : Receive
 *                                  - \ref EMAC_MISTA_CRCEIF_Msk : CRC Error
 *                                  - \ref EMAC_MISTA_RXOVIF_Msk : Receive FIFO Overflow
 *                                  - \ref EMAC_MISTA_LPIF_Msk : Long Packet
 *                                  - \ref EMAC_MISTA_RXGDIF_Msk : Receive Good
 *                                  - \ref EMAC_MISTA_ALIEIF_Msk : Alignment Error
 *                                  - \ref EMAC_MISTA_RPIF_Msk : Runt Packet
 *                                  - \ref EMAC_MISTA_MPCOVIF_Msk : Missed Packet Counter
 *                                  - \ref EMAC_MISTA_MFLEIF_Msk : Maximum Frame Length Exceed
 *                                  - \ref EMAC_MISTA_DENIF_Msk : DMA Early Notification
 *                                  - \ref EMAC_MISTA_RDUIF_Msk : Receive Descriptor Unavailable
 *                                  - \ref EMAC_MISTA_RXBEIF_Msk : Receive Bus Error
 *                                  - \ref EMAC_MISTA_CFRIF_Msk : Control Frame Receive
 *                                  - \ref EMAC_MISTA_WOLIF_Msk : Wake on LAN
 *                                  - \ref EMAC_MISTA_TXIF_Msk : Transmit
 *                                  - \ref EMAC_MISTA_TXUDIF_Msk : Transmit FIFO Underflow
 *                                  - \ref EMAC_MISTA_TXCPIF_Msk : Transmit Completion
 *                                  - \ref EMAC_MISTA_EXDEFIF_Msk : Defer Exceed
 *                                  - \ref EMAC_MISTA_NCSIF_Msk : No Carrier Sense
 *                                  - \ref EMAC_MISTA_TXABTIF_Msk : Transmit Abort
 *                                  - \ref EMAC_MISTA_LCIF_Msk : Late Collision
 *                                  - \ref EMAC_MISTA_TDUIF_Msk : Transmit Descriptor Unavailable
 *                                  - \ref EMAC_MISTA_TXBEIF_Msk : Transmit Bus Error
 *                                  - \ref EMAC_MISTA_TSALMIF_Msk : Time Stamp Alarm
 *
 *    @return       None
 *
 *    @details      This macro get specified interrupt flag or interrupt indicator status.
 *    \hideinitializer
 */
#define EMAC_GET_INT_FLAG(EMAC, u32eIntTypeFlag)    (((EMAC)->MISTA & (u32eIntTypeFlag))?1:0)

/**
 *    @brief        Clear specified interrupt flag/status
 *
 *    @param[in]    EMAC            The pointer of the specified EMAC module
 *    @param[in]    u32eIntTypeFlag Interrupt Type Flag, should be
 *                                  - \ref EMAC_MISTA_RXIF_Msk : Receive
 *                                  - \ref EMAC_MISTA_CRCEIF_Msk : CRC Error
 *                                  - \ref EMAC_MISTA_RXOVIF_Msk : Receive FIFO Overflow
 *                                  - \ref EMAC_MISTA_LPIF_Msk : Long Packet
 *                                  - \ref EMAC_MISTA_RXGDIF_Msk : Receive Good
 *                                  - \ref EMAC_MISTA_ALIEIF_Msk : Alignment Error
 *                                  - \ref EMAC_MISTA_RPIF_Msk : Runt Packet
 *                                  - \ref EMAC_MISTA_MPCOVIF_Msk : Missed Packet Counter
 *                                  - \ref EMAC_MISTA_MFLEIF_Msk : Maximum Frame Length Exceed
 *                                  - \ref EMAC_MISTA_DENIF_Msk : DMA Early Notification
 *                                  - \ref EMAC_MISTA_RDUIF_Msk : Receive Descriptor Unavailable
 *                                  - \ref EMAC_MISTA_RXBEIF_Msk : Receive Bus Error
 *                                  - \ref EMAC_MISTA_CFRIF_Msk : Control Frame Receive
 *                                  - \ref EMAC_MISTA_WOLIF_Msk : Wake on LAN
 *                                  - \ref EMAC_MISTA_TXIF_Msk : Transmit
 *                                  - \ref EMAC_MISTA_TXUDIF_Msk : Transmit FIFO Underflow
 *                                  - \ref EMAC_MISTA_TXCPIF_Msk : Transmit Completion
 *                                  - \ref EMAC_MISTA_EXDEFIF_Msk : Defer Exceed
 *                                  - \ref EMAC_MISTA_NCSIF_Msk : No Carrier Sense
 *                                  - \ref EMAC_MISTA_TXABTIF_Msk : Transmit Abort
 *                                  - \ref EMAC_MISTA_LCIF_Msk : Late Collision
 *                                  - \ref EMAC_MISTA_TDUIF_Msk : Transmit Descriptor Unavailable
 *                                  - \ref EMAC_MISTA_TXBEIF_Msk : Transmit Bus Error
 *                                  - \ref EMAC_MISTA_TSALMIF_Msk : Time Stamp Alarm
 *
 *    @retval       0 The specified interrupt is not happened.
 *                  1 The specified interrupt is happened.
 *
 *    @details      This macro clear specified interrupt flag or interrupt indicator status.
 *    \hideinitializer
 */
#define EMAC_CLEAR_INT_FLAG(EMAC, u32eIntTypeFlag)    ((EMAC)->MISTA |= (u32eIntTypeFlag))
#define EMAC_CLEAR_ALL_INT_FLAG(EMAC)                 ((EMAC)->MISTA |= (EMAC)->MISTA)


 void EMAC_Open(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8MacAddr);
 void EMAC_Close(EMAC_TypeDef *EMAC);
 void EMAC_SetMacAddr(EMAC_TypeDef *EMAC, uint8_t *pu8MacAddr);
 void EMAC_EnableCamEntry(EMAC_TypeDef *EMAC, uint32_t u32Entry, uint8_t pu8MacAddr[]);
 void EMAC_DisableCamEntry(EMAC_TypeDef *EMAC, uint32_t u32Entry);

 uint32_t EMAC_RecvPkt(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t *pu32Size);
 uint32_t EMAC_RecvPktTS(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec);
 void EMAC_RecvPktDone(EMAC_MEMMGR_T *psMemMgr);

 uint32_t EMAC_SendPkt(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t u32Size);
 uint32_t EMAC_SendPktDone(EMAC_MEMMGR_T *psMemMgr);
 uint32_t EMAC_SendPktDoneTS(EMAC_MEMMGR_T *psMemMgr, uint32_t *pu32Sec, uint32_t *pu32Nsec);

 void EMAC_EnableTS(EMAC_TypeDef *EMAC, uint32_t u32Sec, uint32_t u32Nsec);
 void EMAC_DisableTS(EMAC_TypeDef *EMAC);
 void EMAC_GetTime(EMAC_TypeDef *EMAC, uint32_t *pu32Sec, uint32_t *pu32Nsec);
 void EMAC_SetTime(EMAC_TypeDef *EMAC, uint32_t u32Sec, uint32_t u32Nsec);
 void EMAC_UpdateTime(EMAC_TypeDef *EMAC, uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec);
 void EMAC_EnableAlarm(EMAC_TypeDef *EMAC, uint32_t u32Sec, uint32_t u32Nsec);
 void EMAC_DisableAlarm(EMAC_TypeDef *EMAC);

 uint32_t EMAC_CheckLinkStatus(EMAC_TypeDef *EMAC);

 void EMAC_Reset(EMAC_TypeDef *EMAC);
 void EMAC_PhyInit(EMAC_TypeDef *EMAC);
 int32_t EMAC_FillCamEntry(EMAC_TypeDef *EMAC, uint8_t pu8MacAddr[]);
 uint8_t *EMAC_ClaimFreeTXBuf(EMAC_MEMMGR_T *psMemMgr);
 uint32_t EMAC_GetAvailRXBufSize(EMAC_MEMMGR_T *psMemMgr, uint8_t **ppuDataBuf);
 uint32_t EMAC_SendPktWoCopy(EMAC_MEMMGR_T *psMemMgr, uint32_t u32Size);
 void EMAC_RecvPktDoneWoRxTrigger(EMAC_MEMMGR_T *psMemMgr);

/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */

/*@}*/ /* end of group EMAC_Driver */

/*@}*/ /* end of group Standard_Driver */

#ifdef __cplusplus
}
#endif

#endif /* __NU_EMAC_H__ */

/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
